In this visible role, you will be responsible for taking part in a SoC verification process of a large-scale SoC. You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply sophisticated techniques to achieve verification with the highest quality, efficiency, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post Silicon Validation.
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In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, and de-bug the test failures. Develop block, IP, and SoC level test benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.
Requirements: Minimum Qualifications:
Pursuing for BSc in Electrical engineering, Computer Engineering.
Preferred Qualifications:
Previous demonstrated internship or project work in the above fields - advantage.
Experience with C/C++, Verilog, VHDL, scripting languages is helpful.
Knowledge in Verilog- Advantage.
This position is open to all candidates.