As a Graph Compiler Software Manager, you will lead the development of next-generation graph compiler technology. This compiler is a cornerstone of AI software offering, empowering customers to optimize, map, and execute complex neural networks across architectures with extraordinary efficiency. You will lead a group of talented engineers and team leaders working across domains such as compiler optimizations, graph-level transformations, operator mapping, scheduling, and code generation. We are seeking a visionary and technically strong leader with passion for excellence and impact in one of the most fascinating areas of AI and deep learning.

Key Responsibilities:

Lead the design and implementation of innovative graph compilation flows for AI workloads, from high-level optimizations to hardware-specific backends. Build and guide a strong, innovative, and results-driven compiler team that thrives on solving complex technical challenges. Collaborate with hardware architecture, VLSI, and software framework teams worldwide to ensure seamless integration and maximum performance. Lead the end-to-end delivery of graph compiler components while meeting aggressive KPIs. Establish and execute group planning processes to ensure timely and high-quality delivery. Provide technical and managerial guidance to team leaders and engineers. Define and drive compiler optimization strategies for AI and deep learning workloads.

The AI Graph Compiler Engineer will design and develop next-generation graph compiler technologies enabling efficient execution of advanced AI models on Neural Processing Units (NPUs) used in edge and embedded AI devices. In this role, you will work at the intersection of AI frameworks, graph optimization, and hardware acceleration, enabling efficient execution of neural networks on cutting-edge AI hardware.

You will work at the intersection of AI frameworks, compiler infrastructure, and hardware acceleration, helping translate high-level AI models into highly optimized executions on NPUs.



What will you do:

Develop and enhance AI graph compiler components targeting NPU architectures. Implement graph-level optimizations such as operator fusion, scheduling, memory planning, and layout transformations. Participate in lowering models from AI frameworks (e.g., PyTorch, ONNX, TensorFlow) into NPU-optimized representations. Contribute to compiler passes focused on performance, memory efficiency, and numerical correctness. Collaborate closely with hardware, runtime, and AI framework teams to achieve optimal end-to-end performance. Analyze performance bottlenecks and assist in compiler-based optimizations. Debug and resolve issues across compiler, runtime, and hardware layers. Support testing, validation, and documentation of compiler features.

In this role, you will be a key contributor to the design and implementation of AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.

You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of NPU embedded solutions, actively promoting AI capabilities to the customers.

What will you do:

Own and design key components of the AI Graph Compiler software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.

In this role, as Embedded Software Team Leader, you will lead a software team taking major part in developing AI framework. This framework is at the heart of the AI software offering, with deep impact on multiple hardware and software teams ability to execute state of the art LLM, Generative AI and Neural Networks with extraordinary performance. You will lead a team of creative and result oriented enthusiasts that invent, design, and implement software that enables smooth connectivity between the NPU and Host CPU.

Key Responsibilities:

Lead and manage the Embedded Software engineering team, ensuring high performance and productivity. Oversee the design, development, and implementation. Collaborate with cross-functional teams to integrate solutions. Provide technical guidance and mentorship to team members. Ensure project timelines and deliverables are met. Conduct performance reviews and support professional development of team members. Collaborate globally with architects, HW teams, NPU teams, and other developer teams.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for an outstanding Senior Technical instructor to join our Education Services team. In this role, you will provide advanced training on our data center, AI, and HPC platforms to customers and partners around the world. You will also contribute to developing training content, including presentation decks, hands-on manuals, and supporting materials. You will help engineers, architects, and operations teams build the skills needed to design, deploy, and operate our-powered AI data centers with confidence. As part of this, you will take part in the design of hands-on workshops and lab environments that simulate real systems and data center components, enabling learners to practice on realistic end-to-end scenarios.

What youll be doing:

Deliver in-person and remote technical training on our data center, AI, and HPC platforms for customers and partners, with up to 25% travel as needed.

Lead lab-based training sessions that walk learners through end-to-end workflows on our GPUs, DGX/GB200 systems, high-speed networking, and AI/HPC software stacks.

Collaborate with internal experts and content developers to build agendas, exercises, and demos that reflect real customer use cases and guidelines.

Serve as a subject-matter guide (SME) for a dedicated production team and learning developers. They build primary content. Partner with them on slideware, lab guides, videos, simulations, visual demos, and exercises. Ensure technical accuracy and realism.

Act as a technical ambassador for us in front of partner and customer audiences, answering inquiries, facilitating discussions, and guiding learners through fix and what-if scenarios.

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology.

Define of hardware and system architectures.

Research and evaluate algorithms currently used in related applications.

Develop complex proof-of-concepts to demonstrate ideas.

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology

Define of hardware and system architectures

Research and evaluate algorithms currently used in related applications

Develop complex proof-of-concepts to demonstrate ideas

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

seeking a hands-on Embedded Software Technical Lead to play a key role in the design and development of firmware for our next-generation rider products. This role is focused on deep technical ownership, system -level thinking, and high-quality implementation, and is ideal for an experienced Embedded engineer with a strong algorithmic background and solid architectural understanding-who can also mentor and lead a small team of 2-3 Embedded engineers while remaining highly hands-on in day-to-day development. What Youll Do
* Take hands-on responsibility for the design and implementation of Embedded software architecture for new wireless communication devices (ARM Cortex-M, RTOS, ultra-low-power systems).
* Design, implement, and optimize complex Embedded algorithms, including Real-Time control flows, communication logic, and audio/ DSP -related pipelines.
* Write, review, and maintain high-quality, production-grade C / C ++ code.
* Contribute to system -level architectural decisions and ensure scalable, robust firmware design.
* Define and promote coding standards, design patterns, and best practices across the firmware domain.
* Act as a technical focal point for debugging, root-cause analysis, and performance optimization of complex issues.
* Lead a small team of 2-3 programmers/engineers: provide technical direction, help with task breakdown and prioritization, and ensure high-quality delivery.
* Mentor engineers through design reviews, technical discussions, pairing, and hands-on collaboration-raising the teams engineering bar.
* Work closely with Hardware, QA, Mobile App, Cloud, and Product teams to deliver integrated, end-to-end solutions.
* Participate in technical roadmap discussions and evaluation of tools, technologies, and wireless stacks.

Spectrum-X is our ethernet networking solution for massively scaled AI factories. As the Spectrum-X Integration Engineering manager, you will lead a team to ensure that the solution's software features are developed, tested and delivered to meet the high standards of our customers. Do you want to help create the most exciting solutions in the world of networking today? If so, read on.

What you'll be doing:

Engaging directly with our customers to ensure we are aligned on their networking requirements.

Marshalling a cross-disciplinary team of architects, testers, customer managers, and other software teams to deliver products and features on time.

Defining and reviewing switch architectures and test plans.

Providing expertise on ethernet networking both internally and to customers.