דרושים » חשמל ואלקטרוניקה » Senior VLSI CAD and AI Automation Engineer

EDA/CAD Software Engineer
About The Position
The company designs and builds hardware that fuels advanced privacy technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure cloud computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data-analysis and real-time computing is acceleration - existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us.
Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.
Roles and responsibilities
Build, maintain, and optimize CAD tools supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate design flows spanning frontend RTL-to-GDSII, digital backend implementation, and physical/verification signoff, ensuring scalability and tapeout readiness.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Design and implement testing frameworks, regression suites, code review practices, and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are looking for a Physical Design Engineer
Roles and Responsibilities
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are hiring a senior, hands-on engineer to lead technical innovation in our Design Verification (DV) automation infrastructure. This role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. You will directly influence how verification is performed across our next-generation Networking chips, enabling more scalable, efficient, and robust flows for complex ASICs powering the AI revolution.

What you'll be doing:

Lead the development of advanced verification automation tools, regression flows, and debug infrastructure.

Identify key challenges and inefficiencies in current DV methodologies and proactively propose and implement improvements.

Work closely with DV engineers, design teams, and tool developers to ensure solutions are practical and impactful.

Balance innovation with hands-on engagement in daily DV issues - keeping a strong connection to real-world challenges and support needs.

Act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for DV automation.

we are looking for a Senior CAD Engineer.
What you'll do
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

Required Senior VLSI Backend Engineer
We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

We are searching for a forward-thinking Software Engineer to join our VLSI Design Automation Infrastructure team. We are looking for a candidate who looks beyond traditional scripting and is eager to leverage Artificial Intelligence and Machine Learning to revolutionize how we build chips.

In this role, you will manage high-performance compute and storage environments while pioneering the integration of AI-driven tools into our workflows. You wont just maintain the infrastructure; you will modernize it-using LLMs to optimize code, ML to predict compute bottlenecks, and intelligent automation to streamline the backend networking team's success.

What youll be doing:

AI-Driven Optimization: Leverage AI/ML methodologies to analyze compute and storage patterns, predicting resource needs and optimizing LSF grid performance.

Next-Gen Tooling: Design and develop intelligent scripts and automation tools, integrating Generative AI (LLMs) to accelerate debugging and workflow generation.

Infrastructure Management: oversee complex On-Prem environments (LSF) and storage solutions, ensuring maximum uptime for critical VLSI projects.

Data Visualization: Build dynamic, data-driven dashboards that not only report status but utilize analytics to provide actionable insights on infrastructure health.

we are seeking a motivated and detail-oriented Software Engineer to join our innovative VLSI Design Automation team. This group is responsible for building advanced VLSI CAD solutions and web-based platforms. We are looking for a full-stack engineer who is excited about handling large-scale data, enhancing web performance, and developing intuitive dashboards and applications. The ideal candidate brings solid backend experience, a strong data-driven mindset, a passion for learning, and excellent collaboration skills.
What youll be doing:
Design, develop, test, integrate CI/CD pipelines, deploy, and support features for web applications and dashboards.
Own the services and databases you build.
Identify areas for improving performance and inserting automation.

We are looking for a passionate and experienced software developer to join our Chip Design Technologies group, helping to build the tools that shape the future of Chip Design and Verification. This role is at the intersection of software engineering and hardware design. Youll work on the software that accelerates the development of NVIDIAs industry-leading networking chips - highway for the AI revolution.

We're looking for someone who combines strong coding skills with a solid understanding of chip design or verification. If youre excited about solving technical bottlenecks, building scalable tools, and collaborating with designers and verification experts, youll feel right at home here.

What youll be doing:

Develop software tools for our chip design and verification flows

Collaborate closely with designers and verification engineers to identify bottlenecks, propose improvements, and build software solutions that boost productivity and quality.

Own your solutions end-to-end - from idea to delivery to support.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.