דרושים » חשמל ואלקטרוניקה » Senior System Engineer (HW & Wireless)

we are a dynamic and innovative startup thats digitizing the physical world by turning passive items into active communicators. If you are passionate about building cutting-edge solutions, thrive as a key player in a growing startup thats shaping the future of retail fashion technology bringing GenAI-powered into production - join us to create something remarkable together
We are looking for a System Engineer who "speaks" both Network and Code. In this role, you will be the architect of the systems connectivity, designing how our devices communicate over wired LAN infrastructures and ensuring the software architecture supports robust, high-throughput data flow. You will bridge the gap between IT network configuration and R&D software development.
Responsibilities
System Network Design: Define the networking architecture for complex systems, focusing on Wired LAN configurations, switch management, and topology planning.
E2E device to platform SW features: Collaborate with SW teams to define system-level software features - for example security, configurations, etc...
Network Integration: Lead the integration of system components into customer IT environments (Subnets, VLANs, Firewalls).
Hands-on Coding: Write production-grade code or advanced scripts for system automation, network simulation, and performance testing.
Bottleneck Analysis: Analyze data flows to identify network congestion or software inefficiencies and propose architectural changes.
Security: Define and implement network security protocols (PKI, penetration resilience) within the system design.

Do you want to impact billions of users by developing an extraordinary product with a prime focus on accuracy, understandability and performance of the product?
Bring passion and dedication to your job and there's no telling what you could accomplish.
PHY system engineers are responsible for pre/post-silicon system design activities to achieve full operation and optimization of all PHY aspects of a highly integrated complex wireless communication device.

In this role, you will be part of the team responsible for the PHY system design integration of a WiFi/BT/UWB IC solution. This includes, among other things:
Digital correction methods of RF impairments like Digital pre-distortion, IQ MM correction, Power Control, AGC, Modem control.
Optimizing PHY performance for a given system constraints.
Participate in modem design and implementation, from the architecture stage and floating point implementation all the way to RTL/FPGA validation in fixed point - Debug complex multi-disciplinary issues spanning from RF, PHY, MAC, HW and SW.
Connect with X-functional teams (RFIC, Algo, SW/FW etc.).
Perform hands-on PHY/RF lab work.

We are seeking a highly motivated SoC Architect to join our team and define the next generation of our companys high-performance networking SoCs. Our Ethernet and NVL switch silicon powers the world's most advanced AI compute clusters - from hyperscale GPU systems used to train and inference massive foundation models, to the AI factories shaping the future of computing.
As an SoC Architect at our company, you will drive end-to-end SoC definition, connecting system-level requirements with chip-level implementation across multiple domains. You will work closely with cross-functional teams to craft scalable, power-efficient, and feature-rich SoCs that enable the next leap in networking and AI infrastructure.
What You'll Be Doing:
Lead SoC architecture across multiple teams and disciplines - including firmware, security, debug, power management, and peripheral/IP owners - ensuring holistic architectural alignment and system coherence.
Ensure next-generation architectures meet the requirements and constraints of all stakeholder teams, and drive clear specification and communication of those requirements.
Architect and analyze multi-chip solutions, including die-to-die connectivity, chip partitioning, package/board constraints, system requirements, chip fabric, PCIe subsystem and how SoC subsystems must support them.
Define top-level SoC structure: subsystem partitioning, interconnect, memory subsystem, coherency, clocking, power architecture, and system integration.
Define system flows: power up sequences, boot sequences, software update.
Own the SoC architecture specification and guide it throughout the entire product lifecycle - concept, modeling, implementation, and silicon bring-up.
Perform trade-off analyses across performance, area, power, and feature complexity to drive architectural decisions.
Collaborate deeply with chip architects, logic design, verification, physical design, firmware, and system software to ensure seamless integration of all SoC components.
Contribute to innovation and long-term architectural direction, including patent development.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and OSATs. This is an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will have an understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will help design, deploy and maintain hardware required to screen high performance compute silicon at various stages of the manufacturing pipeline.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage ATE platform setup (including loadboard/probecard design) and change kit, SLT bench platform, and handler.
Identify and screen potential vendors (including technological and budgetary assessment) and track and verify progress at all stages of the design.
Define probecard and loadboard requirements based on testing strategy, accounting for test time, tester memory, and budget.
Review SI/PI simulations and final design signoff.
Validate probecard and loadboard hardware and open testing pipeline.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our company services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and Power Delivery Network (PDN) solutions to achieve optimal Performance-per-Watt.
Architect sophisticated power management policies, including Dynamic Voltage and Frequency Scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power Management Unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of our company's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of our company users.
As a CMOS Technologist and Foundry Engineer, you'll be part of the growing chip design team. In this role, you'll be responsible for driving CMOS (Complementary Metal Oxide Semiconductor) foundry partners, Intellectual Property (IP), and chip design and implementation teams to perform CMOS transistor scaling and Power/Performance Analysis (PPA), and producing technology roadmap benchmarks. You will also be involved in interfacing and driving our design IP partners.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Engage with CMOS foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform PPA simulations on benchmark circuits.
Work with fab partners on device and circuit level test structures, test chips, and characterization and correlation of silicon data. You will use the results of this work to influence design optimizations.
Work with IP partners, design, and physical design teams to design advanced CMOS.
Work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
Work with our commercial and product teams on Foundry and IP vendor management, track technology roadmaps, and determine appropriate technology and IP integration strategies.

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The ML, Systems, and Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.