Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for a DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs. This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:

Develop and maintain simulation infrastructure components for different simulation teams (GPUs, switches, NVLink, Ethernet, PHY) of our high-performance networking chips.

Define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded IPC mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.

Own, extend and optimize all the CI/CD of the simulation team, starting from servers installation to adding and maintaining various Jenkins jobs that help developer and improve their life.

Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.

Support internal users by debugging simulation flows and collaborating on bug resolution.

Take part in future-facing innovation by enabling simulation for next-generation devices and features.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join Beer-Sheva/Tel-Aviv group, working on design in developing RISCV Core for network accelerators.
Design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
Work closely with firmware, software and other groups around the globe.
Work mode: Hybrid home-office.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.

Were hiring an experienced verification engineer to join our team developing advanced telecommunications ASIC/FPGA products. You will join RADs family, as part of our team in Beer-Sheva.



Responsibilities:
Build and maintain verification environments (SystemVerilog/UVM or Specman)
Develop test plans and run constrained-random & directed tests
Debug, analyze coverage, and work closely with design teams
Contribute to methodology and process improvements