דרושים » הנדסה » ATE Design Engineer (IL)

Requirements:
What do we want to see?
A B.Sc degree or above in the field of computer science, electrical and electronic engineering or in a similar background in Research & Development, PhD is an advantage
Profound R&D experience in the field of high-performance computing, networked system and ASIC chips for network
Good theoretical understanding in at least one of the following: computer architecture, distributed system and application algorithms, memory systems and network protocols as well as operating system kernels, micro-architecture of ASIC chips, large scale network and computing bus network stacks.
Proven experience with new technology development initiatives and innovation as well as publications in reputed journals - Advantage
High level of self-reliance and an autonomous target-oriented work style, can do attitude, eager to learn new things and ready to think outside the box
Occasional travel related to ongoing projects, seminars, conferences etc.

Requirements:
MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Minimum of 10 years of proven design experience in complex processor projects.
Familiarity with the ARM architecture and the micro-architecture for current ARM CPU cores.
Software development (C, assembly).
Experience modeling microprocessors using higher-level languages, like C/C++.
Excellent verbal and written communication skills.
Co-operate and communicate well with the architecture team and other members of development team.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to US, Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills
MINIMAL REQUIREMENTS
Solid understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems.
Ability to make trade-offs between power, performance and area appropriately to meet the requirements of the product.
Hand-on experience with high power-efficient CPU core successfully.
Understanding of CPU instruction set architecture and assembly language.
Ownership of the overall verification methodology for a CPU project.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Requirements:
BSc/MSc/PhD in Electrical/Computer Engineering or a related field.
10+ years of experience in VLSI/ASIC design/Chip architecture or micro-architecture of complex blocks.
Experienced in high speed networking (such as: Ethernet Switch, NPU, NIC, Traffic Manager, Fabric Switch, etc).
Skills
Excellent communication skills in English - written and verbal.
Good team player - good team working skills; the ability to work with people at all levels.
Independent and self-learning.
Enthusiastic
Self motivated.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
B.Sc. in Electrical Engineering
Experience in defining architectures DSP/CPU/GPU processor cores is an advantage
Experience in HW acceleration of AI
Architecture modeling experience is an advantage
System C knowledge is an advantage
10+ years in VLSI architecture and design (less can be accepted in case of a unique candidate)
Skills
Good interpersonal skills
Very good technical skills
Team player
Creative
Independent and self-learning.