דרושים » מדעים מדוייקים » Validation Engineer - Quantum Control Systems

we are the global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago.
We are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. we are backed by top-tier investors such as Battery Ventures, TLV Partners, Red Dot Capital, and Avigdor Willenzs investment group.
We are looking for a super talented engineer to join our team and build our company's architectural model of a quantum control system.
We are looking for a motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Working in all fronts - high-level architectural solutions to low-level design constraints
Working across multiple teams and methodologies
Designing a complex IP to be used both internally by various R&D teams and externally for our customers as a stand-alone product
Designing a flexible and integration-able model to allow referencing from various programming languages (UVM, Java, Python, Kotlin and C++) as well as coupling it to a behavioral quantum simulator.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
The hardware development team spans two global sites - one in Tel Aviv and one in Copenhagen. The team is responsible for all hardware within our company spanning from room-temperature control hardware to our cryogenic QPU carriers.
We are looking for a Validation Engineer or Physicist to plan and execute validation activities for cryogenic hardware, with a strong focus on electrical and RF performance. In this role, you will work closely with system architecture, RF, mechanical, and hands-on engineering functions to translate design intent and requirements into validated, production-ready solutions. The position combines structured test planning, shared technical risk ownership, and hands-on execution in laboratory and cryogenic environments.
Key Responsibilities
Define validation strategies, test plans, and acceptance criteria aligned with system and customer requirements.
Contribute to customer-facing compliance matrices and quality planning.
Take ownership of Factory Acceptance Testing (FAT) and Site Acceptance Testing (SAT).
Report on test results and provide clear, actionable feedback to development teams and customers.
Design, build, and maintain electrical and RF test setups, fixtures, and measurements.
Contribute to technical risk analysis at the project level, defining validation and mitigation activities in collaboration with the project team.
Plan and execute proof-of-concept (POC) validation activities, with emphasis on electrical and RF performance.
Perform cryogenic testing, including preparation, operation, data collection, and analysis.

Were looking for a skilled and motivated Verification & Validation (V&V) Engineer to join our multidisciplinary engineering team.
In this role, youll design and execute validation strategies ensuring our advanced computer vision and backend systems meet the highest standards of quality, performance, and reliability. Youll collaborate closely with software, hardware, and research teams to bring our innovative store automation solutions from lab to production.
A day in the life
Design and implement test plans and validation procedures for our AI-based perception and backend systems.
Develop and maintain automated testing frameworks and tools using Python.
Create test scripts to validate end-to-end system performance, functionality, and reliability.
Collaborate with development, product, and operations teams to ensure smooth integration and release cycles.
Analyze test data, identify issues, and work with developers to resolve defects efficiently.
Participate in live store validation and field testing to confirm system robustness in real-world environments.
Contribute to the continuous improvement of testing methodologies and processes.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
We are seeking a highly skilled Hands-On Engineer to join our Quantum Integration Team, ensuring seamless integration of multi-layered systems. This role requires close collaboration with cross-functional teams to debug, validate, and integrate complex interfaces while ensuring end-to-end functionality.
Key Responsibilities:
Integration of multi-disciplinary systems, ensuring smooth operation across different layers.
Debug and troubleshoot issues arising in the integration process.
Develop integration and validation tools.
Collaborate with architecture, logic design, verification, compiler, and embedded teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a research and development team. You will build verification components, constrained-random testing, system testing, and verification closure. You will verify digital designs and collaborate with design and verification engineers in projects and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with strategic value add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are hiring a skilled Senior DPU Performance Validation Engineer for our DPU product lines. This includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. Working in the Network Silicon Engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future our company silicon devices. You will collaborate with Chip Design, Verification, FW, and Architecture teams to ensure successful product development with bold product cycles. The qualified candidate should be comfortable working in Simulation and Emulation environments, with strong skills in RTL-level debug, waveform analysis, and system-level performance root cause analysis.
What you will be doing:
Learn and analyze system-level operation of our company DPUs
Debug and root-cause performance issues in pre-silicon environments, across RTL, waveform traces, and multi-die system simulations.
Collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
Develop and improve validation methodologies for performance experiments and data collection.
Automate repetitive debug and validation tasks to scale coverage and efficiency.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Senior Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include our companyrs, our company Cloud customers, and billions of our companyusers worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Additionally, you will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.