דרושים » הנדסה » Senior ASIC frontend Design Engineer

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities:
Join a team of VLSI frontend design engineers in projects.
Define, plan and implement our next chip in on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilites:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

we are expanding our reach and impact.
Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.
Responsibilities:
Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc)
Full block level timing closure and manufacturing checks signoff including power planning and analysis
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level
Insertion of DFT test structures and chip level integration, capture and simulation
Jointly with management, build your career development and growth opportunities.

We are on the lookout for a dedicated and driven Software Engineer to join our dynamic VLSI Design Automation team. This team focuses on the development of VLSI CAD tools and web applications, and is responsible for managing and maintaining high-quality VLSI infrastructure, including compute and storage for the Backend Networking team. We seek a passionate engineer eager to effectively manage compute and storage, develop scripts, automate processes, and create dashboards and applications. Our ideal candidate is someone with experience in VLSI methodologies, data-driven, eager to learn, and possesses strong interpersonal skills.

What youll be doing:

Oversee and optimize compute and storage resources, ensuring operational efficiency and success of VLSI projects. Develop and maintain scripts and automation tools to streamline infrastructure tasks.

Engaging in the entire lifecycle of tool and web application development, which includes backend, frontend, data storage design, UI/UX design, testing, deployment, and maintenance.

Design, implement, and maintain dashboards for monitoring and reporting on infrastructure performance and usage.

Challenge existing VLSI methodologies to have better tools and flows.

Do you want to help accelerate the networking solution across our product portfolio? Our Co-packaged silicon-photonics group seeks a dedicated R&D system engineer to join our silicon-photonics testing platforms team. We seek a skilled and experienced systems engineer to join our team.

The ideal candidate will have experience in these topics: high-speed testing of fiber-optic modules for telecom/datacom, lasers, and post-silicon verification. In this role, you will lead the design, Integration, and deployment of electro-optical testing platforms for SiPh. You will work closely with the R&D teams, internal verification teams, architects, FW developers, market-leading subcontractors, and other stakeholders to design systems. This role requires hands-on experience and a deep system-level multidisciplinary understanding of high-speed transceivers, as well as excellent integration, problem-solving skills, and strong communication abilities.

What youll be doing:

You will lead the design of testing setups for bringing up and testing the new SiPh transceiver chips.

Provide technical support and assistance to manufacturers of silicon photonics testing platforms.

Troubleshoot and diagnose technical issues related to equipment, processes, and software.

Document experimental procedures, results, and findings accurately and comprehensively.

Collaborate with cross-functional teams, including engineering, product development, and manufacturing, to resolve complex technical issues and implement system upgrades or modifications.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.

We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing ASICs used to accelerate networking in data centers. You will have dynamic, multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.