דרושים » חשמל ואלקטרוניקה » DFT Engineer

we are looking for a highly skilled and experienced DFT Lead to take a central role in shaping the DFT implementation for the companys next-generation SoC. As the DFT Lead, you will be responsible for overseeing the development and execution of testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. You will play a critical leadership role in integrating test structures into the design of electronic components, driving efficient testing processes throughout the product lifecycle, from production to deployment and maintenance. This is a key position that will directly influence the success of our projects and the quality of our products.
Responsibilities
Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, MBIST
Implement and validate DFT features to ensure coverage and quality.
Perform scan insertion, MBIST insertion and ensure architectural spec is met
Generate ATPG patterns for stuck at and at speed, ensure all sequential elements are scannable to achieve high coverage. Generate MBIST patterns and ensure all memories are being covered for defects
Collaborate with design teams to create test strategies and plans that identify potential defects
Perform simulations and verification of DFT designs to confirm functionality and accuracy.
Analyze fault models and optimize for high coverage, including stuck-at, transition, and path delay faults.
Collaborate with test engineers to perform yield analysis and improve DFT methodologies.
Troubleshoot and debug design issues found during testing.
Develop techniques to isolate faults and improve test coverage with minimal impact on design.
Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively.
Document DFT architecture, procedures, and test coverage to support production testing and ongoing improvement.

new ideas have a way of becoming products, services and customer experiences very quickly.
Every single day, people do amazing things Imagine what you could do here!
Do you want to impact billions of users by developing an extraordinary product with a prime focus on accuracy, understandability and performance of the product? You will become part of a hands-on development team that fosters engineering perfection, creativity and innovation. Dynamic, encouraging people and innovative technologies are the norm here. Join us and youll help us innovate new wireless systems technologies that continually outperform the previous iterations. By collaborating with other product development groups across, youll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world.

We are looking for Wireless Embedded RF Firmware Engineer. We are the center of the embedded 5G/4G/multimode cellular firmware effort within a silicon design group responsible for designing and productizing state-of-the-art cellular SoCs. This position requires someone comfortable with all aspects of embedded software development, that thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly and is flexible enough to pivot on constantly evolving requirements.
Description
Specify, design, and implement the RF firmware architecture of a state-of-the-art mobile wireless communications system
Design, develop and optimize RF algorithms
Implement RF device drivers and control software for RF transceivers and RF front end components with precise timing requirements
Work with cross functional teams to define HW/SW interfaces and manage dependencies

As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

we are looking for a Senior Silicon DFT Lead, Google Cloud
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Required SoC Physical Design Engineer, Electrical Analysis
Imagine what you could do here! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Hardware products. The same passion for innovation that goes into our products also applies to our practices, strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking product! As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC.
Description:
As a member of our physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise, and Signal EM.
You will work with the CAD/technology teams for flow bring-up and validation.
You will also collaborate with the implementation team during the entire chip design cycle to drive sign-off closure for tape-out.
You will handle schedules and support cross-functional engineering efforts.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

we relentlessly strive to create products that enrich peoples lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out..
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.

Our Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.