דרושים » מדעים מדוייקים » Verification engineer SoC group

Requirements:
Ph.D. or Masters degree in electrical engineering, computer engineering, mechatronics, etc.
Proficient in digital/analog circuit design, signal integrity and power integrity knowledge, high-speed digital circuit design; familiar with CPU, FPGA, power supply, clock, memory, reliability analysis, etc.
Previous experience in breakthroughs of key technologies, such as high-speed and high-efficiency motion mechanism design, vibration and noise suppression and isolation, simplistic design for cost optimization, etc.
Proficient in the design and development of servo drive & controller hardware for automation; previous experience in leading the cutting-edge servo drive & controller R&D in the industry; previous experience in leading high-speed & high-precision automation architecture and solution design; capable of breaking down component performance indexes and solving problems for industry automation equipment
Proficient in automation hardware selection and sizing, as well as circuit simulation; familiar with hardware design, manufacturing, and tuning process.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.

Requirements:
5+ years of experience in high-speed SERDES design, implementation, or research, with hands-on involvement in previous generations of Ethernet standards (e.g., 100G, 200G, 400G).
Proven experience with IEEE 802.3 working groups and standards, particularly in areas related to Ethernet and optical PHY layer technologies (e.g., 802.3ba, 802.3bs, 802.3cd, 802.3ck)
Deep knowledge of modulation techniques such as PAM4 and NRZ, as well as high-speed signaling protocols used in both optical and copper interconnects
Expertise in physical layer research, signal integrity, channel modeling, equalization and error correction techniques for high-speed links
Experience working with key industry players, vendors, and consortiums to shape standards and drive technology adoption
Strong ability to produce technical reports, white papers, and presentations that distill complex technical information into actionable insights
How would you stand out:
Advanced Degree: Masters or PhD in Electrical Engineering, Communications Engineering, or a related field
Expertise and knowledge in in PCS/PMA sublayers, GMII Interface and MAC (Media Access control) in IEEE 802.3.
Extensive involvement in developing Ethernet standards from 100G up to 400G, with insights into the evolution toward 800G and Terabit Ethernet
Demonstrated leadership in managing cross-functional engineering projects related to PHY layer technologies and SERDES interface innovation
Previous experience presenting at or contributing to major industry conferences and events (e.g., OFC, ECOC, IEEE Ethernet Alliance meetings).

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.

Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.