דרושים » חשמל ואלקטרוניקה » Lead Verification Engineer

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חברה חסויה
Location: Caesarea
Job Type: Full Time
we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
Advantages

2+ years of managerial experience. (Only for DV lead)
Knowledge in Low Power technics and UPF standard.
Knowledge with Mix signals SoCs.
Knowledge with SW/HW Co-development
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
We're seeking a driven and experienced Digital Designer to join our dynamic team and contribute to our cutting-edge battery-less Ultra low-power System-on-Chip (SoC) project. If you have a minimum of 3 years of hands-on experience in SOC design and a strong desire to innovate, we want to hear from you!

Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities
Requirements:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in SOC design
Strong understanding of digital design principles and CMOS technology
Proficiency in Verilog or SystemVerilog for design
Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor Graphics).
Knowledge of low-power design techniques (e.g., clock gating, power gating, multi-voltage domains, UPF)
Experience with timing analysis and closure
Excellent problem-solving and debugging skills
Strong communication and teamwork abilities
Advantages: Experience with RISC-V based SoC
Advantages: knowledge of using cdc techniques
Advantages: knowledge of SV-UVM, UPF techniques, CPU (RISC-V), and FW code techniques
Advantages: knowledge of MCU SoC Arch. , Analog ICs, Mix-signals design and Lab equipment.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
We're seeking a driven and experienced Digital Designer to join our dynamic team and contribute to our cutting-edge battery-less Ultra low-power System-on-Chip (SoC) project. If you have a minimum of 3 years of hands-on experience in SOC design and a strong desire to innovate, we want to hear from you!

Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities
Requirements:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum 1+ years of experience in SOC design
Strong understanding of digital design principles and CMOS technology
Experience with timing analysis and closure
Excellent problem-solving and debugging skills
Strong communication and teamwork abilities
Advantages: Experience with RISC-V based SoC
Advantages: knowledge of using cdc techniques
Advantages: knowledge of SV-UVM, UPF techniques, CPU (RISC-V), and FW code techniques
Advantages: knowledge of MCU SoC Arch. , Analog ICs, Mix-signals design and Lab equipment.
This position is open to all candidates.
 
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3 ימים
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time
We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

VLSI group is responsible for the development of our next generation SoC for AI Compute. The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.
Requirements:
7+ years of experience as a Verification Engineer.

B.Sc./M.Sc. degree in electrical/computer engineering from a leading university.

Experience in pre-silicon functional unit level/fullchip verification.

Experience in leading block/cluster verification from scratch.

Experience in System Verilog UVM.

Experience in verification of complex SoC and designs.

Experience with AMBA protocols and NOC subsystem is an advantage.

Experience with CPU subsystem is an advantage.

Experience with PCIe is an advantage
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.
Requirements:
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering or a related field.
Hands-on experience with one or more DFT features, such as scan insertion, BIST, or boundary scan.
Proficiency in full product lifecycle development, from pre-silicon design to silicon bring-up and production qualification.

Preferred Qualifications:
Experience with Automatic Test Pattern Generation (ATPG) methodologies.
Strong ability to establish and refine DFT methodologies from design phase to high-volume production.
Ability to quickly learn new concepts and adapt to evolving technologies.
Excellent communication and presentation skills.
Strong attention to detail and system-level understanding of networking and silicon solutions.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
You'll be joining our Front-End Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
You'll be joining our Silicon One group which is the center of our ASIC design. You'll be part of our Group driving our game-changing next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporation. Our design center is very unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility. We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!
Requirements:
Minimum Requirements:
B.Sc/M.Sc in EE from a top university.
RTL designer experience.
Familiar with UVM and functional testing.

Preferred Qualifications:
Experience in Matlab simulations and Bit Exact environments.
Familiar with mixed Signal systems/environments.
Knowledge & experience with Clock Domain Crossing.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
You'll be joining our Physical Design team within our Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Requirements:
Minimum Requirements
A VLSI Design Engineer with extensive experience in backend design.
B.Sc./M.Sc. in Electrical Engineering.
Strong understanding of Place & Route flow.

Preferred/Advantageous Qualifications:
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
Join the Silicon One team in developing a unified silicon architecture for web-scale and service provider networks.
Our silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

Your Impact
Define our Silicon One devices and deliver specifications to other development teams.
Work with internal and external customers to understand and define current and future requirements.
Innovate at all levels to deliver market-first features and solutions.
Conduct in-depth research to shape the architecture of next-generation networking devices.
Contribute to full-chip integration and cross-functional collaborations to enhance design methodology.
Participate in the definition and analysis of networking system solutions, ensuring they meet market and technical needs.
Requirements:
Minimum Qualifications:
Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field.
Strong analytical and research skills with a deep theoretical background in networking.
Experience in system-level architecture and ASIC design process.
Proficiency in software development (C++, Python).
Strong ability to learn and grasp new concepts from papers and specifications.
Excellent presentation and communication skills to convey complex technical ideas effectively.
Proven ability to work independently and drive initiatives without managerial oversight.

Preferred Qualifications:
Experience researching networking solutions and developing innovative system architectures.
Familiarity with silicon design methodologies and the verification/debugging process.
Strong documentation skills for creating technical specifications and architectural documentation.
Ability to collaborate within a team and contribute to collective goals.
Attention to detail to ensure precision in system-level solutions and architectural decisions.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
The NPI Product Engineer leads the transition from R&D to operations with a focus on SMT processes. This role leads the introduction of new products and supports existing manufacturing operations. The engineer oversees multi-functional collaboration, supplier management, and test equipment projects. Responsibilities include leading product documentation, conducting ECO processes, and implementing FAIs for SMT components. The position requires validating manufacturing processes and providing training in SMT techniques.
You'll be joining our Silicon One team which is the center of our ASIC design.
Our engineers deal with all chip design aspects: from definition, architecture, coding to physical design and signoff.

Lab post silicon electrical characterization very high speed interfaces characterization and compliance to spec, silicon electrical validation including power, speed, process, packaging thermal and more.

High usage with lab high speed / RF equipment and automation.

We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
Requirements:
B.Sc. in Electrical/ Industrial Engineering or equivalent experience.
4+ years in engineering/NPI with a focus on SMT processes.
Project management experience, especially in multidisciplinary products.
Strong communication skills in English and Hebrew.
Leadership and problem-solving abilities within fast-paced SMT production environments.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
You'll join the Front-End Design team, responsible for all chip design processes from definition and microarchitecture to final product.

Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.

We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

You'll be part of our Silicon One group, the hub of our ASIC design.

As a member of our team, you'll contribute to driving our groundbreaking next-generation network devices.
Requirements:
Minimum Requirements:
5+ years experience in digital logic design verification.
Advanced knowledge of SystemVerilog and UVM.
Advanced debug skills pre-silicon and in-lab.

Preferred Requirements:
Scripting abilities.
System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU).
Basic SW knowledge (chop driver level).
Basic design knowledge.
This position is open to all candidates.
 
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