דרושים » הנדסה » Networking ASIC Architect

Join the Silicon One PHY System Team, a key part of our silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.

Your responsibilities will include:

Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY firmware and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.

Who You'll Work With:

You'll work within us, our ASIC design group, contributing to revolutionary network devices.

Operate in a dynamic startup-like atmosphere within a stable and leading corporation.
Collaborate in a design center housing all silicon hardware and software development disciplines under one roof.
Be part of a team transforming the industry with a unified, programmable silicon architecture designed for 5G networks and beyond.

As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

You will join our Silicon One team, the epicenter of our ASIC design.

Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.

Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

You'll be joining our Front-End Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.
We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
You'll be joining our Silicon One group which is the center of our ASIC design. You'll be part of our Group driving our game-changing next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporation. Our design center is very unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale, or feature flexibility. We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

As an Analog Design Engineer, you will:
Design and develop high-speed analog/mixed-signal circuits for industry-leading CMOS process nodes.
Lead all design stages, from architecture definition to final layout sign-off.
Perform circuit simulations, analysis, and debugging to ensure robust performance and reliability.
Collaborate with system architects, digital designers, and layout engineers to optimize circuit performance, power, and area.
Engage in post-silicon validation, debugging, and optimization to enhance circuit functionality.

The NPI Product Engineer leads the transition from R&D to operations with a focus on SMT processes. This role leads the introduction of new products and supports existing manufacturing operations. The engineer oversees multi-functional collaboration, supplier management, and test equipment projects. Responsibilities include leading product documentation, conducting ECO processes, and implementing FAIs for SMT components. The position requires validating manufacturing processes and providing training in SMT techniques.
You'll be joining our Silicon One team which is the center of our ASIC design.
Our engineers deal with all chip design aspects: from definition, architecture, coding to physical design and signoff.

Lab post silicon electrical characterization very high speed interfaces characterization and compliance to spec, silicon electrical validation including power, speed, process, packaging thermal and more.

High usage with lab high speed / RF equipment and automation.

We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

We are seeking an experienced Runtime Software Architect to lead the design and development of an advanced runtime framework tailored for our servers. This role involves analyzing existing runtime systems and machine learning runtime frameworks such as ONNX Runtime onnxruntime.ai, TensorFlow Serving, PyTorch's TorchServe, Apache TVM tvm.apache.org, and Glow github.com, to inform the creation of a new framework that efficiently leverages low-level hardware components, including DSPs, video decoders, ARM cores, and DLAs. The ideal candidate will possess a deep understanding of these technologies and a proven track record in architecting software that harmonizes with complex hardware infrastructures.

Key Responsibilities:
Framework Analysis: Conduct comprehensive evaluations of existing runtime systems and ML runtime frameworks, such as ONNX Runtime, TensorFlow Serving, TorchServe, Apache TVM, VLLM, TRT-LLM, and Glow, to identify their strengths, weaknesses, and applicability to our objectives.
Architecture Design: Develop a robust runtime framework optimized for our servers, ensuring seamless integration with hardware components such as DSPs, video & audio decoders, ARM cores, and DLAs.
Hardware Integration: Collaborate with hardware engineers to adapt and optimize software components, maximizing performance and efficiency across various hardware modules.
Performance Optimization: Implement strategies to enhance system performance, including reducing latency, increasing throughput, and improving resource utilization.
Cross-Functional Collaboration: Work closely with cross-functional teams to align software architecture with business goals and technological advancements.

As BSP / Embedded Team Leader, you will lead a team of talented embedded software engineers responsible for the development, maintenance, and optimization of Board Support Packages for our custom hardware platforms. You will work closely with hardware, kernel, and system software teams to ensure robust and efficient low-level software integration.

Responsibilities:
Lead the BSP / Embedded development team, providing technical direction, mentorship, and guidance.
Design, develop, and maintain BSP components including bootloaders, device drivers, and board initialization code.
Collaborate with hardware teams to bring up new boards and support silicon validation.
Ensure seamless integration of BSP with Linux (or other OS) kernels and embedded software stacks.
Define and enforce coding standards, development processes, and quality benchmarks.
Own the delivery of BSP milestones in alignment with project timelines.
Troubleshoot and resolve low-level system issues and performance bottlenecks.
Stay up-to-date with industry trends, tools, and best practices in embedded systems.

You'll be joining our Hardware architecture team, focusing on advanced modeling and simulation using SystemC.
In this role, you'll contribute to the development of complex infrastructure of SystemC behavioral models.
Your work will enable the infrastructure to support the entire chip design process, enhancing simulation accuracy, performance, and cross-functional collaboration.

We are seeking a highly skilled and experienced Machine Learning (ML) Application Engineer Team Lead to spearhead the development of reference applications in computer vision and large language models (LLMs). This role involves designing and implementing robust ML pipelines utilized by both our customers and internal teams to evaluate and benchmark our hardware/platform. The ideal candidate will lead a team of four engineers, each focusing on individual applications, ensuring synchronization and cohesive progress across projects.

Key Responsibilities:
Team Leadership: Manage and mentor a team of four ML engineers, fostering a collaborative environment that encourages innovation and professional growth.
Application Development: Oversee the design and development of reference applications in computer vision and LLMs, ensuring they meet industry standards and client requirements.
Pipeline Engineering: Develop and optimize ML pipelines for vision and LLM applications, facilitating seamless integration and deployment for customers and internal assessments.
Performance Evaluation: Lead efforts to benchmark our hardware/platform's performance against competitors, providing insights and recommendations for continuous improvement.
Cross-Project Coordination: Ensure alignment and effective communication among team members, synchronizing efforts across various application projects.
Stakeholder Collaboration: Work closely with product managers, hardware engineers, and other stakeholders to align application development with business objectives and technological advancements.