דרושים » חשמל ואלקטרוניקה » Silicon Validation Practical Engineer

Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules, DC tests, binning, production and characterization flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors.
Support product, volume data analysis of screening and characterization data, test time and yield improvements, assess test escapees and Return Materials/Merchandise Authorizations (RMAs), localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to improve and automate the testing.

We are looking for a Senior Test Automation Engineer to join our Product Engineering Team. In this role, you will be responsible for designing and implementing automated test programs for hardware validation and production testing. You will work closely with hardware engineers to define test strategies, ensure seamless SW-HW integration, and optimize test environments to improve efficiency and reliability.

Key Responsibilities

Define and drive team SW methodologies to develop scalable and maintainable test solutions by using SW best practices
Develop and maintain automated test programs for hardware validation and production testing.
Analyze hardware schematics and component datasheets to understand DUT (Device Under Test) behavior.
Collaborate with hardware engineers to define, implement, and stabilize automated test environments.
Enable HW operation through software-driven testing methodologies.
Debug SW-HW integration issues and optimize test sequences for robustness and efficiency.
Maintain test documentation, analyze test results, and contribute to yield improvement efforts.

At our company, we're on a mission to redefine vehicle safety and reliability on a global scale. Founded in 2016, we have pioneered the world's first fully automated suite of vehicle inspection systems. At the heart of this innovation lies our advanced AI-driven technology, representing the pinnacle of Machine Learning, GenAI, and computer vision within the automotive sector. With close to $400M in funding and strategic partnerships with industry giants such as Amazon, General Motors, Volvo, and CarMax, we stand at the forefront of automotive technological advancement. Our growing global team of over 200 employees is committed to creating a workplace that celebrates diversity and encourages teamwork. Our drive for innovation and pursuit of excellence are deeply Embedded in our vibrant company culture, ensuring that each individual's efforts are recognized and valued as we unite to build a safer automotive world.
We are hiring a highly skilled and motivated Electronics Engineer to join our talented Hardware R&D team.
A day in the life and how youll make an impact:
* Develop and own all electrical modules of our products.
* Integrate new components and sensors into the system.
* Perform PCB development activities for new designs and improvements.
* Lead troubleshooting of faulty electrical components.
* Collaborate with system engineers, mechanics, and software teams to develop next-gen features and products.

Build and mentor a high-performing team of silicon validation engineers, and foster a culture of collaboration, innovation, and technical excellence.
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
Lead the debug and resolution of silicon issues, collaborate with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Define and lead qualification hardware and test developments in front of internal teams and external vendors.
Define and execute Silicon and package qualification activities (HTOL, ELFR, ESD/LU, b/HAST, THB, etc.).
Extract, manipulate, and analyze large volumes of data from Silicon and Package qualification programs (e.g. HTOL, ELFR, ESD, LU, UHAST, TCT, etc.), High Volume MFG, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield and quality and reliability improvement.
Own cross-functional investigation of IC quality and reliability issues to identify root causes and develop solutions (RMA Triage, Analytics, Failure Analysis, etc.).
Develop and implement physics-based statistical Quality and Reliability models (ELF, TDDB, NBTI, HCI, Time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

Create software solutions that improve the hardware post-silicon testing process through automation. This includes, but is not limited to, developing and maintaining an ATE program development infrastructure for both production and development environments.
Propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon test flow, from DFT to ATE.
Work directly with a Hardware team on projects - prototype and then deploy tools to make a positive impact on Google's chip hardware development process.
Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies.
Review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).

We are looking for a super talented engineer to join our team and build architectural model of a quantum control system.

We are looking for a motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists

Responsibilities:

Working in all fronts high-level architectural solutions to low-level design constraints
Working across multiple teams and methodologies
Designing a complex IP to be used both internally by various R&D teams and externally for our customers as a stand-alone product
Designing a flexible and integration-able model to allow referencing from various programming languages (UVM, Java, Python, Kotlin and C++) as well as coupling it to a behavioral quantum simulator

Define and implement solutions for complex design, integration and verification problems using in house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Be involved in project development and convergence with the highest quality, work on issues as they arise through design and implementation.
Connect between RTL design, physical design, DFT, external IPs and System on a Chip (SoC) while maintaining project priorities.
Maintain project infrastructure and stability.