דרושים Ready

Requirements:
- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
 - 7+ years of hands-on experience in VLSI Verification
 - Strong knowledge of SystemVerilog and UVM
 - Experience with C / C ++ and Python or PERL - advantage
-  Background in RTL analysis and complex logic verification - advantage

Requirements:
- 2+ years of experience in algorithm development and/or data analysis.
- Proven experience analyzing data and improving/optimizing existing algorithms.
- B.Sc. or higher in Electrical Engineering (EE), Mathematics, Computer Science, Physics, or a related field.
- Proficiency in MATLAB and/or Python (including data libraries such as NumPy, Pandas, etc.).
- Strong analytical and problem-solving skills.
- Experience in DefenseTech systems - a significant advantage.

Requirements:
- 5+ years of experience as a Verification engineer.
- Experience with networking protocols, specifically Ethernet - Must.
- Strong experience with Specman (preferred) OR SystemVerilog / UVM.

Requirements:
- 7+ years of experience as a Verification engineer.
- Proficient in SystemVerilog and UVM methodology - MUST.
- Strong debugging and problem-solving skills.