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As a Senior AI Engineer on the Guardian Agents team, you will develop both our autonomous "digital employees" that execute security programs and the Control Plane that governs them. You will build a platform that allows customers to calibrate agents through conversation, ensuring human feedback is transformed into persistent organizational knowledge. By engineering these closed-loop systems, you enable agents to learn, evolve, and deliver accurate, goal-driven security outcomes at scale.
What Youll Do:
Architect Autonomous Agents: Build goal-driven agents for complex security tasks like false-positive reduction and automated triage.
Build the Control Plane: Develop the infrastructure for Human-in-the-Loop (HITL) feedback, natural language calibration, and stateful memory systems.
Engineer for Growth: Implement evaluation frameworks and "organizational memory" to ensure agents stay accurate and follow historical security precedents.
Bridge AI & Engineering: Collaborate in a "Core Pod" with Security Researchers and Data Scientists to turn raw security signals into scalable, productized agent behaviors.
Scale Data Pipelines: Integrate agents with Big Data foundation to ensure real-time context and tenant-safe execution.

We invite you to join the DP QA department responsible for high end enterprise security solutions. Our cutting edge security platforms simplify operations while ensuring resilience, efficiency, and SLA adherence.

In this role, you will take an active part in mastering our Next Generation Cyber Security products, with a strong emphasis on automation, quality engineering, and the adoption of AI driven testing methodologies.

You will work in an Agile Scrum environment within a dynamic, fast growing, and highly innovative team.

What will you do?
Planning, design, development, reporting, and analysis of manual and automation tests.
End to end testing of various DP features and components.
Building and maintaining automation frameworks for complex networking and security environments.
Utilizing AI powered tools to improve test coverage, defect detection, and root cause analysis.
Developing test insights using AI/ML models for anomaly detection and optimization of regression cycles.
Collaborating with development, QA, and data teams to integrate AI assisted automation into CI/CD pipelines.
Participating in Agile processes, contributing to test strategy and continuous quality improvement.

Founded in Tel Aviv in 2016, UVeye is a computer vision and data company that creates automatic vehicle inspection systems to encourage road safety and increase transparency across the automotive industry. With key partnerships including General Motors, Volvo, and CarMax among others, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more.
With over $380M in funding and strategic partnerships with industry giants such as Toyota, Amazon, General Motors, Volvo, and Hertz, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more. Our growing global team of over 250 employees is committed to creating a workplace that celebrates diversity, encourages teamwork, and strives for excellence.
UVeye is looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
Here’s what you’ll be doing:
* Develop and own all electrical modules for UVeye products.
* Integrate new components and sensors into the system.
* Perform PCB development activities for new and improving the existing.
* Lead troubleshoots of faulty electrical components.
* Cooperate with the system engineer, mechanics, and SW teams to develop next-gen features and products.

Founded in Tel Aviv in 2016, UVeye is a computer vision and data company that creates automatic vehicle inspection systems to encourage road safety and increase transparency across the automotive industry. With key partnerships including General Motors, Volvo, and CarMax among others, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more. Want to be an essential part of setting the standard for safety in the auto industry? Check out the description below to see if you’re a great fit! UVeye is seeking a highly skilled and innovative System Engineer to join our R&D team. The ideal candidate will have a strong background in systems engineering, particularly in optical sensors and visible light cameras. You will play a crucial role in the development and optimization of our multidisciplinary system, ensuring its high performance across various applications.
Here’s what you’ll be doing:
* Develop innovative solutions to challenging customer use cases
* Define system architecture for new products through collaboration with optics, mechanics, electronics, SW and algorithm teams.
* Design and integrate system features, calibrations, and performance optimizations.
* Support existing products, including root cause analysis and solutions to customer issues.

We are looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
Heres what youll be doing:
Develop and own all electrical modules for our products.
Integrate new components and sensors into the system.
Perform PCB development activities for new and improving the existing.
Lead troubleshoots of faulty electrical components.
Cooperate with the system engineer, mechanics, and SW teams to develop next-gen features and products.

We are seeking a highly skilled and innovative System Engineer to join our R&D team. The ideal candidate will have a strong background in systems engineering, particularly in optical sensors and visible light cameras. You will play a crucial role in the development and optimization of our multidisciplinary system, ensuring its high performance across various applications.
Heres what youll be doing:
Develop innovative solutions to challenging customer use cases
Define system architecture for new products through collaboration with optics, mechanics, electronics, SW and algorithm teams.
Design and integrate system features, calibrations, and performance optimizations.
Support existing products, including root cause analysis and solutions to customer issues.

We are looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities
Bring architecture requirements of our AI Chips to a power and area efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with backend and DFT to converge the design into silicon.
Join the bring up of the features with SW when silicon is back in lab and the magic happens.

Required Field Application Engineer - AI Accelerators
In this position:
You will serve as the primary technical interface between us and our customers for our AI accelerator product line and future accelerator platforms. You will support customers through the full product lifecycle - from pre-sale technical engagement and proof-of-concept development through production deployment and ongoing field support. You will work hand-in-hand with R&D to investigate and resolve complex issues, develop reference applications and demos, and act as a trusted technical advisor to both customers and internal teams.
Responsibilities
Develop a comprehensive understanding of each customers use case, system architecture, and integration requirements, serving as their primary technical point of contact for all accelerator-related topics.
Provide deep technical support across the accelerator portfolio, including the Dataflow Compiler, model compilation, and runtime integration.
Reproduce, investigate, and drive resolution of complex hardware and software issues in close collaboration with R&D, spanning PCIe integration, driver-level debugging, inference pipeline optimization, and power management.
Lead technical alignment with customers - clearly communicating issue status, setting expectations, coordinating across internal teams, and ensuring customer satisfaction.
Design and implement customer-facing demo and reference applications in C/C++, showcasing accelerator capabilities at major industry events such as CES and other trade shows.
Support pre-sale technical activities including solution scoping, feasibility assessments, and technical presentations to prospective customers.
Provide knowledge transfer and technical enablement to FAEs and partners to scale field support effectiveness.
Collaborate closely with R&D, Product, and Business teams to translate customer needs into actionable product requirements and roadmap input.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.