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We are seeking a skilled Digital Hardware & FPGA Engineer. Role Overview: Lead development of FPGA components in Embedded systems and advanced hardware infrastructures.

We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.

We are redefining urban mobility by proving that autonomous vehicles can navigate complex environments using vision-only technology.
As our Hardware Systems Integration Engineer, you will be the lead architect responsible for the "nervous system " of our vehicles. You won't just be selecting components; you will be evaluating infrastructure that enables our AI software to see, process, and React to the world in Real-Time.
Responsibilities:
* Vision-Centric Architecture: Lead the selection and integration of high-dynamic-range (HDR) automotive-grade cameras.
* Compute Platform Selection - Evaluate and benchmark high-performance edge platforms (e.g., NVIDIA Orin, Qualcomm Snapdragon, Ambarella, or custom SOC solutions) capable of handling massive parallel video streams with minimal latency.
* Thermal & Power Integrity: Design integration of computing HW into automotive grade environment. This work can be done with external suppliers.
*  system Synchronization: design and ensure sensor synchronization.
* Redundancy Planning: architect fail-operational hardware systems to ensure the vehicle remains safe even if a specific component or communication bus fails.
* Present to and consult with the group leaders as to hardware design trade-offs

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

we are looking for a Hardware Lead Engineer.
As HW Lead Engineer, in the Nitro team, you will be responsible for defining Annapurna Labs Smart Network Interface Card (NIC) design, leading development and validation cycles, and bringing the product to healthy mass production.
Youll provide leadership in new technologies, bringing them to large-scale deployment, in a continuous effort to deliver a world-class customer experience. We offer a fast-paced, intellectually challenging position, where youll work with technical experts, senior leaders, covering multiple technologies. We are changing the industry, and looking for individuals who are ready for this challenge and want to reach beyond what is possible today.
Key job responsibilities:
- Define the architecture and design specifications of next generation K2 Nitro Cards.
- Own full product life cycle, engage with design partners and manufacturing sites to enable high-yield mass production.
- Lead the analysis and debugging of complex design, manufacturing, and integration challenges.
- Continuously design for process optimization to improve product quality, simplify workflows, and accelerate the Nitro card development lifecycle.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.