לוח משרות דרושים Layout

We are looking for a Physical Design Engineer
Roles and Responsibilities
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are looking for Analog Layout Engineer
Roles and responsibilities
Layout design of sensitive analog circuits where you will need to bring state-of-the-art solutions.
In close co-operation with the Circuit Designer, review and analyze complex analog schematics for layout implementation.
Ensures layout designs best functionality and quality by performing all relevant checks like parasitic checks, IR drop and Electromigration, noise and DFM.
Perform post-layout iterations to ensure the best results.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include our companyrs, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
Design and implement efficient power delivery networks power grids to ensure stable power to all parts of the chip.
Develop and validate high-performance, low-power clock networks (e.g., Clock Tree Synthesis (CTS)) to ensure proper synchronization across the entire chip.
Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
Conduct extensive Design Rule Checks (DRC) to ensure the layout adheres to manufacturing rules, performing Layout Versus Schematic (LVS) checks to verify that the physical layout matches the logical design.

We develop cutting-edge technology in Silicon Photonics, revolutionizing connectivity and communication in data centres. Silicon photonics is becoming a standard technology used for high-performance systems, solving challenges of performance, integration, power, and cost. This technology is growing rapidly also in other markets such as Healthcare, LIDARs, and other sensors.
We are looking to solve difficult problems, smartly and simply, by thinking out of the box, leveraging the knowledge and know-how of the team members, and working as a team to create Magic. Our Company culture is characterized by accountability for our ethics, and for being fair to every employee, customer, supplier, and partner. We believe we must work hard and have fun on the way to success.
We are looking for a Photonics Layout Engineer to join our integrated photonics design team - This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.
In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules. You will work closely with device designers, process engineers, and tape-out teams to deliver high-quality layouts of silicon photonics PICs. Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software. Understanding of photonic components, waveguide routing and automated layout generation is a major advantage. You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.
Responsibilities:
Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software. Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.). Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths. Verify layouts using DRC, and LVS to ensure compliance with foundry requirements. Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts. Optimize layouts for performance, yield, and compactness while adhering to technology constraints. Participate in photonic design automation tool development and workflow improvements. Prepare and manage data for tape-out and support mask review processes. Debug layout and rule-check issues and propose corrective actions.