לוח משרות דרושים Layout

we are looking for a senior pcb design layout engineer to join our hardware engineering team at the autonomous vehicle platform department as a key player in the development of next-generation ecu (electrical control unit) for autonomous vehicles. what will your job look like?
working closely with hardware and mechanical design engineers, you'll perform pcb layout our ecus and other products.
complete development of cad layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
be responsible for the design releases required generation of artwork files, odb++, fab drawings, ict report, and electronic pcb documentation.
your designs will need to follow ipc class 3, signal and power integrity constraints, emi/rfi control and automotive regulations.

what you'll be doing:
support and develop solutions that will improve the efficiency and quality of the mixed-signal group.
define, develop, and maintain in-house, along with industrial utilities, solutions for schematic, layout, package and physical-verification in the fields of costume and eda vendor tools (cadence virtuoso, mentor calibre, synopsys icv and more), environment, and general-purpose solutions.
write, customize and debug icv/calibre runsets of drc, lvs, ext.
skill coding including pcells development.
scripting and programing for ad-hoc solutions and wide tasks solutions.
work closely with nvidias world-wide mixed-signal and technology teams.

perform physical layout for mixed-signal functions like pll's, high speed i/o circuits, serdes, general i/o's, esd structures designs in state-of-the-art sub-micron cmos finfet technologies using cadence tools
you will work with asic and mixed-signal engineers to customize designs for integration in vlsi products.
job duties will include floor planning, custom layout and verifying against design rules and schematics, em/ir analysis

come join the team and see how you can make a lasting impact on the world.
what youll be doing:
analyze pcb designs for manufacturability (dfm) and assembly (dfa) and identify issues early in the design cycle.
collaborate with hardware, layout, and manufacturing teams to ensure design intent aligns with production capabilities.
use cad tools such as cadence allegro and siemens valor to review and optimize pcb layouts.
participate in design reviews and cross-functional meetings to address manufacturing constraints and improve design quality.
document and promote best practices and dfm/dfa guidelines across teams.
support root cause analysis and resolution of manufacturing issues during new product introduction.
stay current with industry standards and emerging pcb manufacturing technologies.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
at our networking, we are driven by innovation and excellence. our team in israel is looking for a dedicated chiplet layout owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing: be part of a cross-business-unit team and own the high-speed ip integration.
build a chiplet floorplan layout design from early assembly/planning through implementation and signoff.
work closely with partition owners and full chip sta engineers to assure high quality and timely convergence.
define and implement efficient, high-quality full chip/chiplet physical design tools, flows, and methodologies.
gain hands-on experience implementing the partition-level be design (rtl2gds).

The company develops cutting-edge technology in Silicon Photonics, revolutionizing connectivity and communication in data centres. Silicon photonics is becoming a standard technology used for high-performance systems, solving challenges of performance, integration, power, and cost. This technology is growing rapidly also in other markets such as Healthcare, LIDARs, and other sensors.
We are looking to solve difficult problems, smartly and simply, by thinking out of the box, leveraging the knowledge and know-how of the team members, and working as a team to create Magic. Our Company culture is characterized by accountability for our ethics, and for being fair to every employee, customer, supplier, and partner. We believe we must work hard and have fun on the way to success.
We are looking for a Photonics Layout Engineer to join our integrated photonics design team - This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.
In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules. You will work closely with device designers, process engineers, and tape-out teams to deliver high-quality layouts of silicon photonics PICs. Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software. Understanding of photonic components, waveguide routing and automated layout generation is a major advantage. You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.
Responsibilities:
Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software. Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.). Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths. Verify layouts using DRC, and LVS to ensure compliance with foundry requirements. Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts. Optimize layouts for performance, yield, and compactness while adhering to technology constraints. Participate in photonic design automation tool development and workflow improvements. Prepare and manage data for tape-out and support mask review processes. Debug layout and rule-check issues and propose corrective actions.