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We are looking for a hands-on ETH SerDes Validation Engineer to lead and execute 112G and next-generation 224G SerDes validation activities.
The role involves deep lab work with Keysight test equipment, automation development, and direct execution of compliance and characterization tests according to industry standards.
This position is ideal for an engineer who combines strong signal-integrity fundamentals, standards expertise, and automation-driven validation in high-speed silicon and system environments.
Key Responsibilities
Perform end-to-end validation of 112G / 224G SerDes PHYs at silicon, package, and system levels
Execute compliance, characterization, and stress tests for high-speed serial links
Operate and configure Keysight high-speed test equipment, including:
BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (variable ISI)
Develop and maintain automation frameworks for SerDes validation:
Test setup control
Data collection
Result analysis and reporting
Python
Shell scripts under Ubuntu
SQL skills for data analysis
Execute and analyze:
Eye diagrams, jitter (RJ/DJ/TJ), BER, bathtub curves
CTLE/DFE behavior
TX FIR optimization
Channel loss and margin analysis
Debug signal-integrity issues across:
Silicon
Package
PCB
Connectors and cables
Work according to industry standards, including:
IEEE (112G / 224G PAM4)
Ethernet (802.3ck / 802.3db and beyond)
Collaborate closely with:
Design teams (SerDes / PHY)
SI/PI engineers
System and board design teams
Document test methodologies, results, and recommendations clearly.

We are looking for an experienced and highly skilled Verification Engineer to join a fast-growing and exciting startup in the data-center domain.
You will play a key role in the verification of a complex, high-performance chip, working on challenging problems, influencing methodology, and helping drive quality and efficiency across the project.
Why Join Us?
Work on cutting-edge silicon for data-center applications
High technical bar with real ownership and impact
Opportunity to influence verification architecture and methodology
Collaborative, friendly, and innovation-driven culture.

Were hiring an experienced verification engineer to join our team developing advanced telecommunications ASIC/FPGA products. You will join RADs family, as part of our team in Beer-Sheva.



Responsibilities:
Build and maintain verification environments (SystemVerilog/UVM or Specman)
Develop test plans and run constrained-random & directed tests
Debug, analyze coverage, and work closely with design teams
Contribute to methodology and process improvements

we are seeking best-in-class asic Verification engineers to help deliver the worlds leading cpu's and SOC 's. this position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. we have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
we are building a new group in israel, this group delivers security engines and risc-v processor ips to all of product lines working with all groups around the world. we are looking for inquisitive, motivated engineers with experience to continue to build this new group. as a senior member of our team, you will be responsible for the verification of high-performance, low-power security engines and risc-v processor modules. you will work closely with architects, design engineers, fc Verification engineers, and sw teams.

Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.

Our Networking Software Group is rapidly growing, and we are hiring software engineers for the networking Switch Software Verification team. Come and join a diverse group of engineers spread across the globe who come together in small close knit teams to innovative and develop groundbreaking solutions.

As a member of the team, you will be a part of cutting edge Python-based SW project using advanced techniques such as white box testing, multi-thread environment and more. You will gain unique knowledge of how switch operating system works and how large scale networks are constructed. Teams utilize the latest software engineering methodologies and tools in an agile fashion to release on time. Are you ready for this challenge?

What you will be doing:

Design, develop, optimize and maintain APIs, tools and libraries for Verification networking infrastructure.

Collaborate with team members, Architects, design, QA teams, and customers (both external and internal).

Design, develop, execute and maintain tests automation for release features.