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Required V&V Engineer
Location:
Afek Industrial Park, Rosh HaAyin
Reports to:
DTG Manager (QA)
V&V Engineer ensures that our products meet all system requirements, adhere to specifications, and deliver a high-quality, competitive solution that fulfills customer needs and expectations.
What will you do?
Serve as the Verification & Validation focal point
for a dedicated program within an Agile team.Conduct requirements and PBI analysis , as well as risk assessment and comprehensive test planning.
Design and execute tests at all levels - from software standalone to full system integration, including black box and grey box testing at the system level.
Define and develop automated tests to support both V&V and R&D activities.
Analyze, document, and report test results , ensuring accurate defect logging and tracking to resolution.
Monitor and follow up on defects and open issues through their full lifecycle.
Collaborate with development teams to provide actionable feedback, support fault isolation, and maintain high-quality data handoffs.
Identify and investigate cross-product issues and dependencies.
Support the Service and Field teams in resolving escalated customer issues and contributing to root cause analysis.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure

In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.

seeking a highly skilled and experienced PCIe Validation Engineer to join our Silicon and System Validation team, playing a key role in the companys core products. This position involves building a complex validation environment from scratch for pre and post silicon, defining test plan execution and debugging failures while collaborating with cross-functional teams. In this role, you will take ownership of the validation from Emulation thru bring-up to product release in quality that meets Next silicons standards.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.

Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.

Key Responsibilities:
* Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
* Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
* CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
* Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
* Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.

our companys innovative processors are designed into the advanced cellular systems of most tear-1 carriers .
We are looking for an experienced and creative Verification Engineer to join our Processor Verification Team.
In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.

our networking product engineering team is looking for a TEST development engineer. the position combines an understanding of hw and sw to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers.
what youll be doing:
design and develop automated tests for networking switches while working closely with the hw, asic, and sw engineering teams to achieve a reliable TEST with high coverage
exposed to various aspects of design, dft, and TEST of nvidia's next-generation network products
take a significant part in the definition and development of tests from the development level to the final TEST of network-systems
working with overseas manufacturing teams to increase yields, TEST coverage, and capacity, and reduce production costs

looking for an excellent senior system Validation engineer!
networking division is a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0. we are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.
what you'll be doing:
TEST verification and validation (both hw and sw).
maintain products quality by improving TEST stability, coverage, design, and manufacturing process in mass production.
execute tests in different scopes such: as regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.
troubleshooting and streamlining/optimizing our testing procedures.
support mass production matters.
debugging production bugs and solving them.

our eyeq platform group (epg) is seeking a motivated formal Verification engineer to join our team and contribute to development of hardware verification environments.
this position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
this is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle. what will your job look like:
be the owner of formal verification environment from first draft to sign-off stage
apply formal methods to verify the correctness of various complex digital systems
work with hw architects/designers to define assumptions, rules and cover properties
help define the formal verification methodology and environment to be applied by the team
explore new formal methods and tools
work with tools like cadence jaspergold, verisium manager, xcelium, indago
analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
develop generic formal blocks/functions of commonly used logic, to be later used off the shelf

architect end-to-end system validation strategies for new hardware platforms.
define TEST coverage and validation methodologies.
collaborate with hardware, software, qual and QA teams to align on product requirements and TEST coverage plans.
lead development of automation frameworks and diagnostics tools to enable scalable and repeatable testing.
analyze TEST data to identify root causes, guide debug efforts, and improve validation coverage.
provide technical leadership and mentorship across multidisciplinary teams and represent system TEST considerations in architecture and design reviews.

we are looking for a senior formal Verification engineer for our networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking nic technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our nic team delivers world class cpu interface and offload solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver the best and most widely used high bw ethernet and ib nics in the industry. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of nvidia's core technology.
you will learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.