דרושים » תוכנה » CPU Verification Engineer

This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

The position is relevant to all our sites: Herzliya, Haifa and Jerusalem.

In this role, you will be responsible for ensuring bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage and more.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.

As a formal verification technical lead you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).

Responsibilities
You will be responsible for: Working with our world-classP design engineers to develop a formal micro-architecture specification. Formalizing the refinement from architecture to micro-architecture. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

The Pixel DV group works on complex, large-scale media IPs. We partner with our architecture and design teams to deliver high quality media IP and systems in order to meet the demanding requirements for excellent products, while boosting performance and meeting area and power goals, incorporating new high quality features.

You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design and architecture teams from the early stages of feature definition, to ensure timely delivery of quality designs.
Working with methods to accelerate verification time.
Involvement with Post Silicon Validation and other verification teams.
Candidate should have good interpersonal and collaboration skills, to work with our partner Design and Architecture teams

In this visible role, you will be responsible for taking part of a SoC verification process of a large scale SoC.
You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs.
Working with methods to accelerate verification time.

Imagine what you could do here. At our company, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.
The people who work here have reinvented entire industries with all our Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking our products.

We're seeking a passionate and skilled Embedded Firmware Engineer to play a pivotal role in delivering the next generation of us. In this highly visible position, you'll be at the intersection of hardware and software, collaborating closely with logic designers to deeply understand system-level operations and performance requirements for hardware validation.

In this role, you will develop critical low-level embedded firmware specifically designed to validate hardware functionality, ensure conformance, and drive performance during the bring-up and testing phases of new silicon. This involves designing, developing, and integrating complex drivers, diagnostic tests, and infrastructure essential for SoC bring-up, post-silicon validation, and debugging activities. Ultimately, you'll lead hands-on firmware development, system-level validation, and problem-solving at the hardware-software interface in a dynamic, collaborative environment, with your work directly enabling the successful launch of future our products by ensuring our silicon meets the highest standards.

In this role you'll participate in the architecture of next generations of our ISP, handle RTL implementation of the micro-architecture, participate in clearly defining specification, testing and verification of the designs. You will work in collaboration with CAD & PD teams to implement RTL design into GDS, run various flows and provide guidelines to other designers and participate in establishing CAD and design methodologies for correct by construction designs.
Were not all the same. And thats our greatest strength. We draw on the differences in who we are, what weve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

Responsibilities
As a logic design engineer, you will handle micro architecture & RTL implementation as well as front-end work and top-level aspects of the design, such as performance and more. You will work closely with DV teams to verify blocks and SoCs and with PD for design implementation.

We are seeking a software engineer to build high-performance software models of advanced SoC designs and to help bridge the gap between Software and Hardware, influencing performance improvements, power efficiency, security, and the programming ease of Apple products.
Responsibilities
In this role, you will:
Develop software systems and tools used to bring up the future OS on future SoCs.
Support kernel and driver development on future processor & SoC models.
Work closely with software and hardware teams across product and research groups.
Promote new opportunities and techniques with other groups.

Responsibilities
Help create the next line of our AI products by leading the build of the infrastructure and groundwork they will stand on.
Lead the architecture and delivery of the low-latency middleware layer behind our iOS and macOS data collection and research applications.
Stay hands-on: write code, review pull requests, and debug the hard problems alongside the team. This is not a purely managerial role.
Set technical direction and coding standards across C++, Objective-C/C++, Swift, and Python.
Own the roadmap with research, firmware, silicon, and product partners, and turn ambiguous, ambitious goals into a concrete technical plan.
Drive design and implementation decisions for the applications on top of the middleware, not just the layer underneath.
Mentor and grow a team of strong engineers, and run the design and code reviews that set the culture.
Bring AI-assisted development into the teams daily workflow and show how much a small team can ship.
Work across the whole stack, from high-level software to low-level physics, and connect the disciplines that make it work.

Somewhere between the physics of a sensor and the software people touch, there is a layer that decides whether a breakthrough actually works. That layer is yours.
We're a small, truly multidisciplinary team that spans high-level software down to low-level physics, and we're building the foundation for our next big technology. As a Senior Software Engineer, you'll build the iOS- and macOS-based, low-latency application layer of our data collection and research system. It is the infrastructure that turns raw, real-world signals into the data that trains and validates the next line of our AI products. You'll write the code that makes it all work, and you'll help shape the applications built on top of it.
This is a rare chance to work on something new, from day one, alongside people who see the whole stack.

Responsibilities
Help create the next line of our AI products by building the infrastructure and laying the groundwork they will stand on.
Design and build low-latency middleware components for our-platform applications (iOS and macOS) supporting data collection and research workflows.
Own end-to-end implementation: architecture, coding, debugging, and performance tuning across the application layer.
Contribute to the design and implementation of downstream applications that consume the middleware (not just the plumbing - the product too).
Write robust, production-quality code in C++, Objective-C/C++, and/or Swift for performance-critical and system-level components, and Python for tooling, data processing, and automation.
Collaborate closely with firmware, data, and research teams to ensure the middleware correctly reflects real-world device and sensor behavior.
Use modern AI-assisted development tools as a core part of your workflow - for code generation, debugging, test authoring, and accelerating iteration.
Participate in design reviews, code reviews, and architectural decisions for the broader system.