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We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

You will lead sophisticated, multi-functional programs spanning silicon development, firmware, and system delivery, driving execution from initial concept through production. You will collaborate with engineering and operations teams to deliver high-quality solutions, craft effective processes, and ensure strategic alignment across the organization.

Specific Responsibilities include:

Driving end-to-end program execution for the Silicon One ASIC software ecosystem, including integration with industry-leading network operating systems.
Serving as a key interface for New Product Introduction (NPI) programs for next-generation Cisco Silicon One devices.
Leading cross-functional alignment across engineering teams in a globally distributed environment.
Owning program schedules, milestones, dependencies, risk management, and executive communications.
Partnering with software engineering leaders to ensure tight hardware/software co-development and integration.
Liaising with Cisco internal business units and customers to collect requirements and manage prioritization across competing stakeholder interests.
Driving accountability for outcomes while working through influence in environments with high ambiguity, rapid change, and ambitious timelines.

We are seeking a high-driven, results-oriented multidisciplinary orchestrator to act as the primary catalyst for our development infrastructure. In this role, you will operate at the critical intersection of product strategy, hardware engineering, and lab operations, serving as the connective tissue that aligns disparate teams under a unified goal. You will be responsible for driving cross-functional alignment across the organization, effectively managing stakeholders with differing ownership to ensure infrastructure roadmaps scale alongside product milestones. This position requires a self-starter comfortable pushing for success in ambiguous environments, where you will translate high-level strategy into the tactical execution of the physical and virtual ecosystems that power our development lifecycle.

Your Impact

You will own the end-to-end lifecycle of infrastructure projects, ensuring that our Sanity Test Beds and development environments are optimized to meet aggressive product launch timelines. By bridging the gap between engineering roadmaps and infrastructure requirements, you will serve as the engine that ensures our teams have the right resources at the right time, regardless of technical or organizational complexity.

Key Responsibilities

Strategic Orchestration & Alignment

Unified Roadmap Integration: Translate complex product development roadmaps into long-term infrastructure requirements, driving cross-functional alignment between silicon milestones and lab availability.
Stakeholder Management: Act as the primary liaison between hardware engineering, software development, procurement, and lab operations; navigate competing priorities among stakeholders with differing ownership to keep teams synchronized.
Ambiguity Management: Proactively identify project roadblocks and navigate ambiguous environments to push critical-path dependencies to resolution.
Operational Velocity: Drive continuous improvement in infrastructure processes, identifying and removing friction to increase overall engineering velocity.
Operational Oversight & Execution

Strategic Capacity Planning: Lead high-stakes capacity management efforts, forecasting needs for power, rack space, and compute resources to proactively eliminate infrastructure bottlenecks.
Lifecycle Ownership: Oversee the full lifecycle of infrastructure projects-from initial procurement and technical specification through deployment, validation, and transition to operational readiness.
Visibility & Reporting: Drive the development of dashboards and reporting mechanisms to provide real-time visibility into infrastructure health, ensuring data-driven decision-making across the organization.
Vendor & Asset Optimization: Partner with cross-functional leadership to manage technical specifications, equipment lead times, and hardware lifecycles, ensuring a high-performance, cost-effective infrastructure footprint.

We are seeking a senior embedded software engineer to serve as the technical lead for our embedded team, developing the real-time software at the heart of a first-in-market surgical robotic platform.

This is a hands-on, individual-contributor role: you will help shape the technical direction, make sound engineering decisions, and take ownership of delivering features end to end, while remaining deeply involved in the code. As the system is designed collaboratively by the team, strong cross-team collaboration is as important as individual technical excellence. This is safety-critical software, and we hold a high standard for rigorous design, testing, and code quality.

Responsibilities:

Serve as the technical and feature lead for the embedded team, guiding design decisions and mentoring peers through code reviews (this is not a people-management role).
Drive the design and development of our real-time embedded software, and own the delivery of features end to end.
Uphold a high standard of code quality through code reviews, best practices, and continuous improvement.
Remain hands-on, personally developing the most complex and safety-critical components in C/C++.
Collaborate closely with other teams across the company to ensure technical alignment and shared progress.
Take ownership of delivery, ensuring features are completed on schedule and to the quality this product demands.
Make technical decisions independently where appropriate, while knowing when to involve the wider team.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Firmware Engineer , you will gain experience in system-level design and development of radio coexistence (e.g., WiFi and Bluetooth) in embedded devices. You will develop a deep understanding of data structures, object-oriented design, and system architecture in an embedded environment.

Responsibilities:

Design, develop, and debug embedded firmware using C/C++
Collaborate with cross-functional teams to integrate firmware into end-to-end IoT solutions
Implement and optimize data structures, object-oriented components, and system architecture in constrained environments
Develop and execute unit tests and validation procedures to ensure firmware quality and reliability
Analyze system performance, identify bottlenecks, and propose improvements
Write and maintain scripts (Python) to support development, testing, and automation

we are seeking a highly motivated and experienced Senior Software Engineer for a position focused on developing innovative network device monitoring and visualization solution.
Your Impact

Design and develop visualization capabilities within our SDK environment
Lead the development of a brand-new comprehensive self-monitoring system for network devices from the ground up
Implement a comprehensive model for capturing and managing network state information
Drive cross-team collaboration and technical strategy
Work closely with senior technical leadership
Create and refine technical requirements and system designs
Build new systems and frameworks from the ground up