דרושים » תוכנה » SW Engineering Manager - Performance Modeling

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team
Our team builds firmware, SDKs, simulators, and compilers for the architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for us
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

we are seeking a Lead System Architect to join our system architecture team and help define the next generation of our AI-SuperNIC scale-out chip.
AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.
You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.
Responsibilities:
Lead the software architecture and technical roadmap for or next-generation ultra low-latency AI-SuperNIC software stack, including drivers, firmware, libfabric, and libibverbs.
Define the partitioning and interfaces between hardware, firmware, kernel drivers, user-space libraries, and AI frameworks.
Lead the design and implementation of high-performance networking, RDMA, and GPU-direct communication capabilities.
Drive software support for emerging technologies and standards such as UEC, UALink, MRC and RoCEv2 ecosystems.
Work closely with hardware, system architecture, and VLSI teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership across firmware, driver, and networking software development

Required Software Modeling Team Leader
Job Description
Meet the Team
Join the Silicon One team in developing a unified silicon architecture for web-scale, service provider, and enterprise networks. Our silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact:
As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the SiliconOne family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.
In this role, you will:
Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for SiliconOne devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback.

We are seeking an exceptional Software Team Lead to guide the development of our runtime software stack. This role requires a rare combination of deep technical expertise, hands-on coding ability, and proven leadership experience. You will own the architecture, implementation, and system-level integration of drivers, runtime components, and low-level system software, driving technical excellence and performance across the stack. The ideal candidate thrives under pressure, takes full ownership of outcomes, and sets the bar for quality and innovation in the team.
Responsibilities
Lead and mentor a team of runtime and embedded software engineers, setting the standard for technical excellence.
Define and drive the architecture, roadmap, and performance expectations for the runtime stack, ensuring scalable, robust, and high-performance solutions.
Oversee cross-team software projects from concept through production, while remaining hands-on in coding, debugging, and system bring-up for critical components.
Establish rigorous standards for testing, CI/CD, and software lifecycle processes, ensuring maintainable and reliable delivery.
Conduct architecture and performance reviews, providing decisive guidance in ambiguous or high-pressure situations.
Collaborate deeply with architecture, compiler, hardware, and platform teams to deliver cohesive, system-level solutions.
Provide technical leadership to resolve conflicts, make tough trade-offs, and uphold engineering excellence.
Recruit, mentor, and retain top-tier engineering talent.

we are a leading semiconductor design center, developing SoCs, microcontrollers, and security hardware solutions for tier-1 customers in the computing and server space. As a self-contained R&D center - spanning architecture, chip design, software, and system engineering - we work closely with major US-based OEMs to deliver innovative, semi-custom silicon solutions. We are now extending our portfolio into AI acceleration, developing a next-generation NPU platform aimed at efficient, real-world AI deployment.
?Shape the Future of AI at the Silicon Level We are looking for a visionary Senior Technical Manager to build and lead our AI software stack for our next-generation NPU platform This is a rare opportunity to own the full software layer - from compiler infrastructure to Developer ecosystem - and make a lasting impact on how AI runs on silicon. What You'll Do; Build and lead a highly skilled AI software & algorithms engineering team, establishing engineering standards, development processes, and technical direction Define the end-to-end stack - compiler, runtime, Kernel libraries, and SDK - enabling efficient AI deployment on our NPU Drive AI compiler development using technologies like MLIR, TVM, LLVM or similar infrastructures to translate PyTorch/TensorFlow models into optimized NPU execution Champion model optimization - quantization, pruning, and hardware-aware techniques for maximum performance and power efficiency on the accelerator. Runtime, Drivers, and Firmware Integration - scheduling, memory management, and low-level software for AI workloads on-chip AI Kernel Libraries - Guide the development of highly optimized neural network Kernel libraries and performance-critical primitives tailored to the architecture of the NPU. Developer Ecosystem - Define and deliver the SDK, APIs, and development tools that allow internal teams and external developers to deploy AI models easily on the platform. Cross-Functional Architecture Collaboration - Work closely with silicon architecture and hardware design teams to ensure optimal hardware-software co-design, providing feedback on architecture, performance bottlenecks, and future ISA requirements.

Required Software Engineer, CPU Performance Modeling, Cloud
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
In this role, you will work with System teams and the CPU Architecture team to develop an understanding of the Central Processing Unit (CPU), System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision making. You will correlate performance projections with measured post-silicon data.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU Architecture teams, SoC performance modeling team, and other Software teams.

we are looking for a Senior SW Engineer.
Job Description:
Join a multi-disciplinary team of experts operating at the core of Speedatas software stack
Lead the design and implementation of highly efficient algorithms that maximize our performance
Develop time-critical Python components that translate database operations to performant, hardware-optimized C++
Co-design the next generation of our architecture alongside Hardware & Software engineering leads
Research state-of-the-art algorithms and techniques for data analytics and hardware acceleration
Fly high with the SW, and dive in for a byte of the HW

Our Professional Services is seeking an Experienced system Engineer We are seeking an Experienced system Engineer to join our team and drive the development of diverse, cutting-edge UAV systems.
If you are looking for a meaningful technological journey filled with multidisciplinary challenges, come and be a part of our story. Key Responsibilities:
* End-to-end development of software- and hardware-intensive UAV systems, from solution definition through technical requirements authoring, integration, testing, and customer delivery.
* Leading complex integration processes, including the integration of products, payloads, and airborne subsystems.
* Defining system -level requirements for various components and authoring detailed specifications and technical documentation.
* Leading cross-functional development and integration efforts across diverse engineering teams, including Airborne Software, C2 (Command & Control) Software, Simulators, QA /Testing, Electronics, and more.

Were looking for an experienced and passionate Software Engineering Team Leader to join our Elastic WAF group - the group behind most strategic and modern next-generation WAF product lines within the AppSec organization.
The Foundation team builds the core infrastructure that powers these products. The team is responsible for developing the foundations of new Cloud-Native and SaaS WAF solutions, designed for simple, fast, and DevOps-friendly onboarding and installation. These products deliver best-of-breed security through a modern, scalable architecture and seamless operational experience.
If youre passionate about leading talented engineers, designing scalable systems, and shaping the architecture of cutting-edge security products, wed love to meet you.
Key Responsibility:
Lead a team of 4 skilled developers focused on building and maintaining core components, shared services, and developer tooling.
Lead distributed system design decisions and continuously improve system performance, maintainability, and technical standards.
Design and evolve scalable, multi-tenant SaaS architecture and cloud-native platform services (microservices, APIs, event-driven systems).
Be hands-on with architecture and development in Java, Go, and Kubernetes.
Drive cross-team initiatives that improve development efficiency, reliability, and scalability.
Act as a mentor and coach to help team members grow professionally and technically.
Collaborate with engineering leads and product stakeholders to set technial direction and priorities.
Champion innovation, transparency, and a strong engineering culture.
Ensure reliability and operational excellence, implementing observability (metrics/logs/tracing) and strong incident response practices.

Required Design and Power Methodology Manager, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design and Power Methodology Team Manager within the Server Chip Design team, you will be responsible for managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.