Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.
Responsibilities:
Lead & grow a team of experienced engineers
Develop new hardware simulators and continue evolving existing one.
Collaborate with Architecture, VLSI, and Software teams to drive co-design initiatives.
Provide insights that influence chip architecture, compiler optimization, and system-level performance.
Develop tools that drive the chip development cycle.

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next-generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage, and networking at large scale. We aim to drive innovation and deliver software-defined infrastructure and algorithms for HPC, AI/ML, and Big Data applications.
We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.

What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software.
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU).
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale.
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations.
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads.
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions.
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally.
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction.
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems.

AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.

You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.

Responsibilities

Lead the software architecture and technical roadmap for or next-generation ultra low-latency AI-SuperNIC software stack, including drivers, firmware, libfabric, and libibverbs.
Define the partitioning and interfaces between hardware, firmware, kernel drivers, user-space libraries, and AI frameworks.
Lead the design and implementation of high-performance networking, RDMA, and GPU-direct communication capabilities.
Drive software support for emerging technologies and standards such as UEC, UALink, MRC and RoCEv2 ecosystems.
Work closely with hardware, system architecture, and VLSI teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership across firmware, driver, and networking software development

In this role, as Senior Team Leader of the AI NPU Simulator, you will lead a Group developing a major part of AI simulation framework, in the core of our AI software offering. The AI NPU simulator enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company.

You will drive the development of robust, scalable, and efficient simulation software, working closely with global Architecture, VLSI, and Software teams to shape next generation of AI solutions.

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading software teams, and a track record of delivering complex, state-of-the-art products on time and with high quality. The ideal candidate is execution-driven, innovative, and passionate about building high-performing teams and cutting-edge AI technology.



Responsibilities

Manage and lead two teams (Development + Validation) .

Be accountable for the simulation lifecycle, including architecture, development, validation, and release.

Lead development of advanced simulation models for AI processors.

Own delivery of complex, multi-release roadmaps.

Ensure strong alignment between hardware design, compiler behavior, and simulation models.

Drive system-level correctness and performance accuracy.

Support system bring-up, debugging, and customer-facing activities when needed

Our Professional Services is seeking an Experienced system Engineer We are seeking an Experienced system Engineer to join our team and drive the development of diverse, cutting-edge UAV systems.
If you are looking for a meaningful technological journey filled with multidisciplinary challenges, come and be a part of our story. Key Responsibilities:
* End-to-end development of software- and hardware-intensive UAV systems, from solution definition through technical requirements authoring, integration, testing, and customer delivery.
* Leading complex integration processes, including the integration of products, payloads, and airborne subsystems.
* Defining system -level requirements for various components and authoring detailed specifications and technical documentation.
* Leading cross-functional development and integration efforts across diverse engineering teams, including Airborne Software, C2 (Command & Control) Software, Simulators, QA /Testing, Electronics, and more.

Required Senior Software Engineer, CPU, Cloud
About the job
In this role, you will work at the center of our most strategic infrastructure investments. You will join a high-impact team operating on the critical path of our hardware and software evolution, bridging the gap between compute infrastructure and the massive scale of our software stack. You will be responsible for defining the methods and technologies required to model, simulate, and analyze complex hardware systems, with a core focus on security, performance, and correctness analytics, ensuring the efficiency of our future compute platforms. As a software engineer in this group, you will act as an architect, designer, and coder taking ownership of your goal and working in close partnership with cross-functional teams to make it a reality.
You will be at the intersection of hardware design and software optimization for our next-generation high-performance compute cores. You will not just support existing infrastructure; but will be helping build the foundation of our future hardware. Because this work is on the "most critical path" for our future, you will have visibility into and influence over the core technology that powers our most intensive services. You will bridge the gap between silicon-level security research and massive-scale software implementation, working with experimental AI tools that are shaping how we verify and optimize future hardware. You will be building the foundation of our future hardware.
Responsibilities
Drive performance modeling and analysis for next-generation CPUs, while identifying architectural bottlenecks, ensure system correctness, and implement optimization strategies across hardware-software stack to maximize efficiency for compute workloads.
Design, develop, and maintain software modeling tools and simulation environments, leverage C++, Python, and AI-driven methodologies to perform studies and automate analytical workflows.
Conduct security analysis and threat modeling for hardware-software interfaces, while developing and implementing methodologies for detecting, mitigating, and analyzing side-channel and micro-architectural vulnerabilities, ensuring systems meet safety and privacy.
Explore, deploy, and scale experimental AI-driven tooling to automate verification workflows, enhance predictive modeling, and accelerate development cycles, actively contribute to expanding the team's suite of AI-assisted capabilities.
Provide technical leadership in system integration projects, guide cross-functional teams to resolve large-scale compute bottlenecks, influence architectural designs, and facilitate the successful deployment of hardware-software solutions.

Lead a team of compiler engineers responsible for open source based toolchain and graph compiler. You will be a hands-on team leader - driving architecture decisions, guiding engineers, and delivering compiler capabilities across all hardware targets. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for a leader who champions this approach.

Responsibilities

Lead development of open source based toolchain targeting custom DSP and NPU architectures. Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation. Champion AI-agentic development practices within the team - integrating AI coding agents into day-to-day engineering workflows. Mentor engineers and conduct code reviews; build a high-quality engineering culture. Collaborate with hardware architecture, algorithms, and software teams globally. Own team planning, prioritization, and on-time delivery of toolchain features. Contribute hands-on to design, implementation, and performance tuning in C++ and Python.

we are looking for a Software Modeling Team Leader.
As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the Cisco SiliconOne family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.
In this role, you will:
Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for Cisco SiliconOne devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback

We are looking for a Principal Engineer with deep expertise in database internals, system architecture, and hardware-aware performance optimization.
This role is responsible for defining and driving advanced database performance solutions by understanding and improving the interaction between database engines, operating systems, and modern hardware architectures.
The ideal candidate is an experienced technical leader with a strong background in database systems, performance engineering, and computer architecture. The candidate should be capable of leading complex technical initiatives, influencing architectural decisions, and developing innovative solutions for next-generation database platforms.
This is a hands-on technical leadership role requiring expertise across database kernels, query execution, transaction processing, memory systems, and low-level performance optimization.

Responsibilities
Define and drive technical direction for database performance optimization and hardware-aware database architecture.
Lead the design and implementation of advanced database optimizations focused on scalability, efficiency, and workload performance.
Solve complex performance challenges across the full system stack, including database engines, query execution, transaction processing, concurrency control, storage engines, operating systems, and hardware platforms.
Design and develop optimizations leveraging modern hardware architectures, including multi-core CPUs, large-memory systems, NUMA platforms, CXL memory, RDMA networking, and advanced storage technologies.
Improve database execution engines, caching mechanisms, memory management, storage systems, and workload scheduling.
Analyze system behavior and identify bottlenecks using profiling, tracing, hardware performance counters, and low-level performance analysis.
Develop benchmarks, workload models, and methodologies to evaluate scalability, efficiency, and architectural tradeoffs.
Collaborate with database kernel, infrastructure, and engineering teams to influence architecture decisions and deliver high-impact improvements.
Mentor senior engineers and contribute to building technical expertise across the organization.
Drive innovation through research, prototyping, technical analysis, and architectural improvements.