דרושים » אבטחת איכות QA » ATE - Test Engineer

we are looking for a Chip Test Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Required Senior Hardware Test Engineer
Description
The Senior Hardware Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
Role and Responsibilities:
Test Development & Validation:
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI):
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement:
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration:
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

Required SoC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

We are looking for a Test Automation Engineer to join our Product Engineering Team. In this role, you will be responsible for designing and implementing automated test programs for hardware validation and production testing. You will work closely with hardware engineers to define test strategies, ensure seamless SW-HW integration, and optimize test environments to improve efficiency and reliability.
Key Responsibilities
Develop and maintain automated test programs for hardware validation and production testing.
Collaborate with hardware engineers to define, implement, and stabilize automated test environments.
Enable HW operation through software-driven testing methodologies.
Debug SW-HW integration issues and optimize test sequences for robustness and efficiency.
Maintain test documentation, analyze test results, and contribute to yield improvement efforts.

Required Senior SOC DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Were looking for a talented Hardware Engineer to join our innovative team.
Responsibilities:
Design, develop, and validate hardware boards for advanced radar and chip-based systems, with a strong focus on digital circuitry and power supply design.
Perform hands-on lab work (HO), including board bring-up, debugging, troubleshooting, repair, and continuous improvement of existing hardware.
Define, write, and execute comprehensive test plans and test setups for board-level validation.
Analyze test results, characterize performance, and document findings, including detailed test reports, failure analysis, and corrective actions.
Support schematic design activities and contribute to the development and maintenance of design environments and databases for EDA tools.
Experience with SI/PI simulation tools.
Collaborate closely with lab technicians, engineers, and cross-functional teams to ensure efficient execution of lab activities and project goals.
Take an active role in prioritizing tasks, driving technical decisions, and owning deliverables end-to-end.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match - powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
- Micro-architecture definition.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

Required RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. You will develop/define design options for performance, power and area.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.

we are looking to hire a talented VLSI DFT Engineer to join our VLSI group in Tel Aviv. You will work alongside other talented engineers to develop our cutting edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Develop and deliver production test patterns (ATPG), including stabilization, coverage analysis, and debug
Analyze silicon failures and drive debug across DFT, design, and test flows
Collaborate with design teams to implement and optimize unique DFT architecture and methodologies (scan, MBIST, etc.)
Participate in pre-silicon verification of DFT features and flows
Contribute to end-to-end DFT flow, from implementation through silicon bring-up