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27/04/2026
Location: Haifa and Tel Aviv-Yafo
Job Type: Full Time
As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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27/04/2026
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.
Requirements:
Basic Qualifications
- 8+ years of experience in logic design.
- 8+ years experience in chip architecture and micro-architecture.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own and technically lead engineering teams.
- Strong knowledge of IO and network protocols.

Preferred Qualifications
- Strong knowledge of chip interconnect protocols (AXI, CHI).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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01/04/2026
חברה חסויה
Location: Haifa
Job Type: Full Time
As a Senior DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization

Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation

Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of hands-on experience in DFT roles at semiconductor companies
Deep expertise in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
Proficiency with industry-standard EDA tools from Synopsys (TestMAX) or Mentor (Tessent)
Strong understanding of logic design, verification, debug, and Static Timing Analysis (STA)
Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation
This position is open to all candidates.
 
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01/04/2026
חברה חסויה
Location: Haifa
Job Type: Full Time
As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter
Requirements:
B.Sc. in Electrical Engineering or Computer Engineering
8+ years of deep, hands-on experience in Static Timing Analysis (STA) at leading semiconductor companies, specifically working on advanced process technologies
Deep expertise in multi-scenario STA, timing/SDC constraint development and verification. You have a "full-chip" perspective, managing both complex macro-level designs and top-level integration
Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
Solid knowledge of physical design flows (P&R, Physical Verification) and how they intersect with timing closure
This position is open to all candidates.
 
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01/04/2026
חברה חסויה
Location: Haifa
Job Type: Full Time
As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of experience in logic design at semiconductor companies
Knowledge and experience in Verilog and/or SystemVerilog
Excellent communication skills with ability to work effectively across teams
Understanding of digital design principles and RTL coding best practices
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
At Lumissil, we are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, Lumissil is the place to develop your skills, innovate, and grow your career. Why join us?
* Work on cutting-edge automotive projects
* Learn from a talented and supportive team
* Gain exposure to real-world automotive challenges
* Grow your career in a collaborative and inspiring environment If you’re ready to take the next step in your career and be part of something meaningful, we’d love to meet you! About The Position: As a Junior ASIC Design Engineer at Lumissil, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where you’ll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions
* Support and learn from real emulation platforms used in production-grade designs
* Contribute to RTL implementation and gain practical experience in design flows
* Assist with verification and backend (BE) activities, learning industry best practices
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.
Requirements:
* B.Sc. in Electrical Engineering (graduate with excellence)
* Strong interest in ASIC / chip design and hardware development
* Basic understanding of RTL design concepts – an advantage
* Any exposure to programming or scripting (e.g., Python, TCL, Perl) – an advantage
* Previous academic or practical experience in relevant fields – an advantage
* Good English communication skills, both written and verbal
* Team player with a positive attitude, curiosity, and willingness to learn
This position is open to all candidates.
 
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01/04/2026
Location: Haifa
Job Type: Full Time
we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration
Requirements:
B.Sc. or M.Sc. in Electrical Engineering
5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration
This position is open to all candidates.
 
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27/04/2026
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor our cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.
Requirements:
Basic Qualifications
- B.Sc. in Computer Science/Computer Engineering/Electrical Engineering or related field. Make sure to include a grade sheet with your CV in a single PDF.
- Knowledge of C programming language.

Preferred Qualifications
- Experience in embedded SW Development.
- Hands-on experience developing in a Linux environment.
- Experience with HW/SW interfaces at both the board and chip level.
- Understanding of computer architecture.
- Personal characteristics: team player, highly motivated, willing to work in a dynamic and demanding environment, creative, and a fast learner.
This position is open to all candidates.
 
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01/04/2026
Location: Haifa
Job Type: Full Time
we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient
Requirements:
B.Sc. in Electrical Engineering or Computer Engineering
5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies, specifically working on advanced process technologies. (Note: Adjust years of experience based on the exact level you are targeting)
Deep expertise in multi-scenario STA, as well as timing and SDC constraint development and verification at the block and subsystem levels
Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off
Solid knowledge of physical design flows (Synthesis, P&R, Physical Verification) and how they intersect with timing closure
This position is open to all candidates.
 
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01/04/2026
Location: Haifa
Job Type: Full Time
we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Requirements:
B.Sc. or M.Sc. in Electrical Engineering
15+ years of hands-on experience in Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills
Deep expertise in RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs
Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
Experience managing both complex Macro-level designs subsystem level and Full-Chip integration
This position is open to all candidates.
 
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01/04/2026
חברה חסויה
Location: Haifa
Job Type: Full Time
we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of hands-on experience in Physical Design at semiconductor companies
Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
Experience working with advanced process technologies (7nm and below)
Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks
This position is open to all candidates.
 
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עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
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