דרושים » הנדסה » Senior Asic Design

Join the Front-End Design team, at the core of our development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.

Your Impact:

Review micro-architecture specifications.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

Your Impact:

Review micro-architecture specifications.

Supervise verification team members and provide professional guidance.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

Required Logic Design Engineer
Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities.

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of our platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products.
Design, document, and develop ASIC subsystems for release in high volume and quality.
Help define the process, methods, and tools for design and implementation of complex developments.
What Youll Do:
Executes assignments delegated in ASIC team.
Owns portion of project code.
Creates own code.
Participates in code reviews.
Debugs owned code.
Contributes to the creation of new designs.
Maintains and enhances existing designs.
Executes test plans and test benches.
Modifies and enhances test to meet specific test cases.
Executes and tests analog/mixed signal products.
Creates floor planning and timing closure of multiple ASIC blocks.
Debugs timing issues with RTL block owners.
Leads products to manufacturing, identifies and helps to implement power and signaling solutions.
Supports with the planning of signal integrity.

Join the PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.

We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.

Your Impact:

Develop PHY firmware and system-level features for advanced networking ASICs.

Design and implement PHY calibrations and system definitions.

Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis.

Collaborate closely with PHY, system, firmware, and silicon design teams.

Contribute to defining system operation modes and end-to-end device behavior.

Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies.

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.