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1 ימים
Location: Be'er Sheva
Job Type: Full Time
We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs. This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.

What Youll Be Doing:

Develop and maintain simulation infrastructure components for different simulation teams (GPUs, switches, NVLink, Ethernet, PHY) of our high-performance networking chips.

Define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded IPC mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.

Own, extend and optimize all the CI/CD of the simulation team, starting from servers installation to adding and maintaining various Jenkins jobs that help developer and improve their life.

Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.

Support internal users by debugging simulation flows and collaborating on bug resolution.

Take part in future-facing innovation by enabling simulation for next-generation devices and features.
Requirements:
What We Need To See:

Bachelor's Degree or equivalent experience in Computer Science / Software Engineering / Computer Engineering / Electrical Engineering / Communication Engineering.

5+ years of experience in Python, C/C++ programming, with strong object-oriented design skills and performance-sensitive environments.

Experience debugging using debuggers (gdb), including concurrency issues (races, deadlocks...).

Strong background with Linux systems, CI/CD pipelines - and automation frameworks (e.g., Jenkins, Git, Docker, Pytest).

Familiarity with Inter-Process Communication (IPC) mechanisms (sockets, message queues, shared memory...).

Ability to communicate complex technical ideas in simple terms.

Well-organized, proactive and capable of leading your own tasks.

Collaborative personality with a love for teamwork.

Ways to Stand Out from the Crowd:

One man show, Swiss knife - you have experience in many areas, you have been through multiple head scratching bugs and rewritten same system multiple times learning from each iteration.

Experience building complex simulation or emulation systems, especially those simulating hardware behavior.

Background with multi-platform systems spanning HW, FW, and SW.

Experience with low-level networking protocols and applications.

A passion for building internal tools that prioritize authenticity, stability, and usability.
This position is open to all candidates.
 
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4 ימים
חברה חסויה
Location: More than one
Job Type: Full Time
Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for a DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.
Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of hands on DFT/ATPG knowledge & technical experience in DFT ASIC Design and in ATPG tools.

Strong programming skills in scripting languages.

Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility.

Ways to stand out from the crowd:

Knowledge of DFT including scan, MBIST, LBIST, on-chip scan compression, fault models, ATPG, and fault simulation.

Experience in Mentor TestKompress ATPG tool and retargeting flow.

Programming languages: TCL, PRL, Phyton & Unix shell scripts.

Experience with ATE and Silicon bring-up.
This position is open to all candidates.
 
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4 ימים
חברה חסויה
Job Type: Full Time
We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join Beer-Sheva/Tel-Aviv group, working on design in developing RISCV Core for network accelerators.
Design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
Work closely with firmware, software and other groups around the globe.
Work mode: Hybrid home-office.
Requirements:
What we need to see:
B.SC./M.SC. or equivalent experience in Electrical Engineering/Communication Engineering/Computer Engineering.
5+ years of validated experience in RTL Frontend ASIC design (Chip Design).
High Level of English.

Ways to stand out from the crowd:
Experience in RTL Frontend ASIC Design.
Knowledge in Verilog.
Experience with physical design aspects.
This position is open to all candidates.
 
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7 ימים
חברה חסויה
Job Type: Full Time
We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
2+ years proven experience in chip design.
Solid hands-on RTL design skills in System-Verilog.
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.

Way to stand out from the crowd:
Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.
This position is open to all candidates.
 
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13/01/2026
חברה חסויה
Job Type: Full Time
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

7+ years of actual design experience in chip design.

Strong RTL proficiency in SystemVerilog for reading/debugging designs and implementing CDC/RDC-safe structures.

Experience with constraints and timing intent (SDC) and their interaction with CDC/RDC.

Hands-on expertise with industry CDC/RDC tools (e.g., SpyGlass, Questa CDC, Real Intent) and lint/formal where relevant.

Proficiency in at least one scripting languages like Python, bash, Perl, TCL.

Great teammate.

Way to stand out from the crowd:

Passion for quality. Experience with delivery to physical design and other customers.
This position is open to all candidates.
 
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27/01/2026
חברה חסויה
Job Type: Full Time
We are seeking a highly skilled Linux Kernel Engineer to join our innovative and dynamic team. In this role, you will be responsible for the development, optimization, and maintenance of Linux kernel components, device drivers, and system-level services.
You will work closely with cross-functional teams to enhance system performance, debug complex kernel-related issues, and contribute to the development of cutting-edge embedded and server-side solutions.
If you are passionate about low-level system development, Linux internals, and making a real impact on the performance and security of modern computing, we want to hear from you!
The position can be based at either Headquarters (Tel-Aviv) or Negev (Beer Sheva).
Responsibilities:
Develop, optimize, and maintain Linux kernel modules, device drivers, and system services.
Troubleshoot and debug kernel-level and low-level system issues to improve system stability and performance.
Work with Linux networking, memory management, and process scheduling to enhance system capabilities.
Integrate and customize open-source components into Linux-based environments.
Collaborate with hardware, firmware, and application teams to develop efficient and scalable solutions.
Ensure security, performance, and reliability of kernel and system services.
Conduct code reviews, testing, and debugging to maintain high-quality software development standards.
Stay up to date with the latest developments in the Linux kernel, system services, and embedded technologies.
Requirements:
B.Sc./M.Sc. in Computer Science, Electrical Engineering, or a related field.
5+ years of experience in Linux kernel development and device driver programming.
Proficiency in C programming and experience with kernel debugging tools.
Deep understanding of Linux internals, including process scheduling, memory management, and file systems.
Experience developing and maintaining system-level services (systemd, daemons, init scripts, etc.).
Hands-on experience with hardware interfaces, buses, and protocols (PCIe, I2C, SPI, USB, etc.).
Experience with bootloaders (e.g. U-Boot) and low-level system bring-up - an advantage.
Familiarity with Buildroot or other embedded Linux build systems - an advantage.
Knowledge of real-time Linux, security hardening, and performance tuning - an advantage.
Experience with open-source contributions - an advantage.
This position is open to all candidates.
 
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2 ימים
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering.

You should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including ERC, LVS and DRC, is necessary.

In-depth knowledge of advanced silicon process technologies.

Familiarity with physical build EDA tools, including Synopsys and Cadence.

A great teammate who thrives in a collaborative environment.

AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:

Experience in Linux environments.

TCL, Python, shell scripting abilities.

Experience with data collection and analysis.

Understanding of the chip and die verification process.
This position is open to all candidates.
 
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1 ימים
Location: Be'er Sheva and Yokne`am
Job Type: Full Time
As the Technical Program Manager in our Infrastructure-RESS IT PMO team, you will be responsible for leading IT infrastructure programs for Office, Lab and Data Center projects: new build, expansion, retrofit, relocation and de-commissioning. You will clarify and challenge objectives, develop roadmaps, assess the complexity and risks, unblock as needed, and partner with highly skilled technical resources to deliver quality solutions with agility and speed. In partnership with senior IT leaders, you will be responsible for global execution of your programs, ensuring consistency and timely execution in line with our PMO processes. You are required to inspect and assess programs health; provide input for improvements needed or seek support in a timely manner for quick resolution.

What you'll be doing:

Lead multiple, concurrent, large and complex programs or projects. Lead the planning, execution, and monitoring of our site IT infrastructure.
Develop project plans along with agreed upon timelines, provide cost estimations, procure IT assets required for the infrastructure programs, guide implementation or deployment of IT assets on site, track timelines, ensure thorough UAT is conducted at the site and do spot tests as TPM, provide hyper care with all functional teams and resolve UAT issues, and ensure adherence to project objectives.
Work with project owners to identify project scope, define success criteria, build and manage project budget, and outline resource requirements. Identify & manage multi-functional dependencies.
Main responsibilities include collaborating with the real estate and facilities leadership group within the region, coordinating with various IT teams such as network active, network passive, storage, compute, end-user support & A/V, procuring required IT assets for all functions and participating in the setup and management of labs and infrastructure at different sites across North America.
Communicate with stakeholders regularly to manage expectations and to provide project updates on scope, budget, and velocity - Real Estate leaders & project managers, site leaders, lab owners, vendors, consultants, implementation partners, etc.
Reporting: Involve project steering committee for guidance and key decisions. Provide quality status reports consistently. Interact and collaborate with multi-functional teams and different org levels.
דרישות:
What we need to see:
Bachelor's Degree in computer science, telecommunications, electronics or other related technical subject area (or equivalent experience)
12+ years of Technical Program Management experience in successfully leading IT Infrastructure programs for Offices and Data Centers; in a fast paced, multi-faceted, enterprise environment
Strong communication skills both written and verbal/presentations. Ability to bridge from high-level objectives to project details and vice-versa. Ability to produce good Status Reports on a weekly and monthly basis. A good command over English language is a must
Ability to engage with IT & business leaders to unblock/advance projects as needed. Strong stakeholder management skills are required
Willingness to work with distributed team members across different time zones
Ability to work with AI tools such as: Co-pilot, Gemini, Chat GPT, Perplexity, Cursor, etc.
Business travel is required, with an estimated travel of once a quarter, for about 2 week, primarily to locations and offices within Israel

Ways to stand out from the crowd:
Ability to drive large transformation programs at scale & behave as an owner. Collaborate with internal teams, external vendors, and business partners to gather requirements, address concerns, and ensure alignment with project objective
Champion effective communication and lead collaborator expectations throughout the project lifecycle. Agile execution expertise a must. Use of Atlassian tools such as Jira and / or Jira Align is a must
Proven track record of delivering solutions when המשרה מיועדת לנשים ולגברים כאחד.
 
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05/01/2026
Location: Be'er Sheva
Job Type: Full Time
We are looking for a highly skilled Integration & Validation Engineer to join our R&D

team and take part in developing our ultra-deep-tech innovative products and solutions for wireless

energy transfer systems for autonomous robotics. The team deals with multidisciplinary R&D tasks for

developing in-house solutions and platforms. Come work with us in a dynamic working environment

with high responsibility, joining us, youll have the chance to develop unique products from scratch to

mass production.

Key Responsibilities:

● Plan, execute and analyze end-to-end systems/products including hardware & embedded

integration tests.

● Designing and building test setups from the first-level design, testing and studying E2E system

operation at nominal and corner scenarios.

● Be a major part of product HW design, including characterization, implementation, and testing.

● Knowledge of all systems, use-cases, installations, and interfaces.

● Close work with HW/Mechanical/Embedded/ASIC and production teams.

● Reliability and compatibility tests according to regulatory requirements.
Requirements:
● B.Sc. in Electrical engineering.

● Specializing in Power Electronics - advantage

● At least 5+ years of experience as an Integration/SystemHW Engineer - Must

● Experience with multi-disciplinary systems - must

● The position requires strong hardware capabilities - Experience with lab equipment for hardware

bring-up and validations - must.

● Strong E2E system/product bring-up and validation capabilities.

● High documentation capability.

● Experience with automation scripts coding - advantage.

● Experience in EMI/EMC - advantage.

● Experience with wireless power charging - huge advantage.
This position is open to all candidates.
 
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05/01/2026
חברה חסויה
Location: Be'er Sheva
Job Type: Full Time
seeking a hands-on Team Leader to lead the integration of our advanced wireless power technology into robotic platforms (AMR/AGV) in real-world industrial environments. This role combines mechanical, electrical, and system-level work, with significant on-site involvement, including visits to customer sites for installations, system reviews, and performance evaluations.

Key Responsibilities:



● Lead a small multidisciplinary team responsible for integrating wireless-power modules into autonomous robotic platforms.

● Perform mechanical and electrical integration, wiring, and assembly on various AMR/AGV systems.

● Conduct on-site installations, field testing, and system commissioning at customer facilities.

● Evaluate robotic platforms from multiple vendors to ensure optimal compatibility with technology.

● Collaborate closely with R&D, hardware, and software teams to refine integration processes and support product evolution.

● Provide technical feedback and documentation based on field experience.

● Support live demos, pilots, and customer evaluations of the system.
Requirements:
● B.Sc. in Mechanical, Electrical, or Mechatronics Engineering.

● 5+ years hands-on experience integrating systems in the robotics or automation industry.

● Familiarity with AMR/AGV platforms and industrial robotic ecosystems.

● Strong understanding of both mechanical design and electrical systems.

● Practical field experience with installations, wiring, and testing.

● Excellent communication and problem-solving skills.

● Travel to customer sites (domestic and abroad).

● Team-oriented attitude and ability to lead by example in a dynamic environment.

● Fluent in English (spoken and written).
This position is open to all candidates.
 
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18/01/2026
Job Type: Full Time and Internship
We are looking for a Formal Verification Developer

Nvidia Networking Formal Verification tool development team is growing and looking for an outstanding computer scientist to join the team as a key player. Our main goal is to develop state of the art formal verification technology. This position offers the opportunity to have real impact in a dynamic, technology-focused company.

What you'll be doing:
Develop formal verification technologies.
Carry innovative ideas from research through development and up to acceptance by team of formal verification engineers.
Collaborate with different teams in the organization to provide end to end formal solutions.
Requirements:
What we need to see:
MSc Graduate in Computer Science, and currently pursuing PhD.
Experience in algorithm development.
Excellent programming, debugging and code design in C++.
Clever with sharp learning curve.
Strong interpersonal skills, both written and verbal.
Ability to work independently with minimal direction.

Ways to stand out for the crowd:
An advanced degree in formal verification or static analysis.
Experience in formal verification development.
This position is open to all candidates.
 
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