דרושים » ייצור ותעשייה » IC Production Manager

A problem isnt truly solved until its solved for all. Thats why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
As a Technical Program Manager for Silicon engineering, you will use your technical and management experience to justify, plan, coordinate, and deliver custom silicon products. You will plan programs and manage their execution from early concepts through development to tapeout and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Justify, plan, and coordinate the delivery of custom silicon products, ensuring they meet technical specifications and business objectives.
Drive alignment and collaboration across the internal silicon ecosystem from design and verification to supply chain and quality to ensure seamless execution and operational readiness.
Lead the development of credible schedules and milestones, proactively identifying technical or timeline risks and negotiating trade offs between what is needed and what is possible.
Guide the selection, qualification, and management of external partners serving as the primary technical and program interface.
Negotiate agreements and Statement of Works (SOWs) while managing vendor performance, quality, and costs to protect the supply chain against disruptions and capacity constraints.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and OSATs. This is an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will have an understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will help design, deploy and maintain hardware required to screen high performance compute silicon at various stages of the manufacturing pipeline.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage ATE platform setup (including loadboard/probecard design) and change kit, SLT bench platform, and handler.
Identify and screen potential vendors (including technological and budgetary assessment) and track and verify progress at all stages of the design.
Define probecard and loadboard requirements based on testing strategy, accounting for test time, tester memory, and budget.
Review SI/PI simulations and final design signoff.
Validate probecard and loadboard hardware and open testing pipeline.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of our company's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of our company users.
As a CMOS Technologist and Foundry Engineer, you'll be part of the growing chip design team. In this role, you'll be responsible for driving CMOS (Complementary Metal Oxide Semiconductor) foundry partners, Intellectual Property (IP), and chip design and implementation teams to perform CMOS transistor scaling and Power/Performance Analysis (PPA), and producing technology roadmap benchmarks. You will also be involved in interfacing and driving our design IP partners.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Engage with CMOS foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform PPA simulations on benchmark circuits.
Work with fab partners on device and circuit level test structures, test chips, and characterization and correlation of silicon data. You will use the results of this work to influence design optimizations.
Work with IP partners, design, and physical design teams to design advanced CMOS.
Work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
Work with our commercial and product teams on Foundry and IP vendor management, track technology roadmaps, and determine appropriate technology and IP integration strategies.

AWS Utility Computing (UC) provides product innovations - from foundational services such as our companys Simple Storage Service (S3) and our company Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, our company Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Annapurna Labs develops the semiconductor platforms of the future for AWS, creating amazing products with complex architectures that push the boundaries of many fields. our company Web Services, the world's largest cloud provider, offers a highly reliable, scalable, and cost-effective infrastructure platform that powers hundreds of thousands of businesses in more than 190 countries. This is an exciting opportunity to join our company and contribute to bringing our next-generation products for the cloud market to the production stage.
Key job responsibilities
Analyze foundry Wafer Acceptance Test (WAT) data from development, corner lots, and qualification lots.
Collaborate with Test Engineering (TE) and Quality & Reliability (Q&R) teams to ensure test quality.
Recommend test plans and limits for production lots, corner lots, and pre-/post-qualification lots based on system specifications, yield, and Cpk targets.
Identify quality and reliability concerns and collaborate with TE, Q&R, and Failure Analysis (FA) teams to drive resolution.
Manage Continuous Improvement Process (CIP) activities with the foundry.
Drive test-time reduction activities based on Wafer Sort (WS) and Final Test (FT) production data.
A day in the life
As a Senior Product Engineer, you will play a crucial role in ensuring that the production of Annapurna Labs semiconductor products meets our customers' demands. Your responsibilities will include monitoring and analyzing production data, collaborating with various teams including Test Engineering and Foundry, Quality & Reliability (Q&R), Failure Analysis (FA), leading process and yield improvement initiatives
optimizing throughput, enhancing test quality, and reducing test time.
In this role, you will be fully exposed to the semiconductor production flow of all Annapurna Labs products, all semiconductor testing methodologies, and FAB process yield improvement activities.

Annapurna Labs, as part of our company, is looking for a System Integration Lead to be part of defining, shaping and integrating solutions for next generation of our cloud platforms. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies.
Key job responsibilities
As System Integration Lead Engineer, you'll drive product development from initial architecture discussions through design, production, and customer deployment. You'll own critical hardware and software system integration, including architecture definition, mechanical design, thermal/power optimization, and signal integrity for high-speed interfaces (PCIe, SATA, Ethernet). Your responsibilities extend to developing robust boot flows, recovery mechanisms, remote debugging capabilities, firmware update processes, and comprehensive health monitoring systems.
You'll design and implement screening tests for production and data centers, lead fleet-level debugging, create repair procedures that maximize capacity recovery, and conduct game-days to validate failure recovery before general availability. This role requires you to define and document integration methodologies that scale across our product portfolio.
You'll lead the application of emerging technologies to large-scale deployments, directly impacting customer experience. In this fast-paced position, you'll collaborate with technology leaders across disciplines while maintaining exceptionally high standards. We seek candidates who consistently find ways to improve performance, quality, and cost-efficiency as we transform our industry.
If you're ready to push beyond today's limitations and solve complex integration challenges at scale, this role offers the opportunity to make a significant impact.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-Specific Integrated Circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation-based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, supporting the hardware and lab bring up, and verifying our ASIC systems.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation EDA tools, licensing, and job management in our company infrastructure.
Support emulation team members with debugging hardware, tooling, and project-specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Annapurna Labs, part of AWS, seeks a Nitro Integration Engineer to scale and simplify Nitro hardware integration across manufacturing and data center environments.
You will design tools, automation, and standardized integration flows that make Nitro integration reliable, repeatable, and scalable. Your work will enable internal teams and partners to integrate Nitro hardware efficiently while maintaining quality and consistency.
Working across hardware, firmware, software, manufacturing, and operations teams, you will transform complex integration challenges into robust, production-ready solutions.
Key job responsibilities
- Design and maintain self-service tools for Nitro card integration, validation, and health monitoring.
- Enable customers to independently configure RAMDisk, enable K2, and perform validation tasks.
- Create intuitive, reliable workflows with clear documentation for self-service Nitro integration.
- Identify friction points and improve tooling, processes, and system design.
- Ensure self-service features maintain quality parity with managed processes.
- Implement metrics and monitoring to track adoption and performance.
- Resolve technical escalations for self-service tool issues.
- Develop strategies to increase customer autonomy while reducing operational load.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities:
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.
Act as Functional Safety manager, leading the definition, execution and oversight of functional safety strategy and processes-ensuring compliance with standards (such as ISO 26262), driving hazard and risk analyses, coordinating cross-functional teams, and embedding safety-culture across product development.

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.