דרושים » ניהול ביניים » VLSI design engineer

Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SoC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe

Requirements:
A VLSI Design Engineer with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevent background.
​ 5+ years of hands-on experience in a relevant domain
Strong understanding of Place & Route flow
Preferred qualifications:
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently

Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.

Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.

Requirements:
B.Sc. in Electrical Engineering from a recognized institution.
Minimum 7 years of hands-on experience in microarchitecture and RTL design.
At least 3 years in a leadership role managing ASIC teams or projects.
Experience in leading ASIC programs from concept through production.
Deep understanding of the entire ASIC development lifecycle and its technical requirements.
Solid experience in digital IP and SoC design, verification, and implementation methodologies.
Proficiency in industry-standard EDA tools for Lint, CDC analysis, simulation, debugging, synthesis, and timing closure.
Excellent communication and interpersonal skills.
Preferred Skills & Experience
Familiarity with functional safety (ISO 26262).
Experience with multi-core SoCs and security architectures (e.g., HSM).
Background in computer vision, DSPs, or automotive systems.
Knowledge of automotive protocols (CAN, Automotive Ethernet, FlexRay, AutoSAR).
Experience with embedded software and low-power design techniques.
Prior collaboration with external back-end design teams.
Exposure to optical systems is a strong advantage.

Requirements:
At least 3+ years experience with RTL2GDS flow

BSC/MSC in Electrical/Computer engineering

Deep understanding on STA principals, synthesis, and P&R flow

Solid experience in physical verification and advanced process nodes

Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of System Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SoC architecture, CPU subsystems, and multi-core designs.

Requirements:
Required:
At least 5 years of experience in digital design for ASIC.
BSc/MSc in Electrical Engineering, Computer Engineering, or related field
Strong RTL development experience in Verilog/SystemVerilog.
Solid understanding of computer architecture, logic design, and digital system fundamentals.
Experience with micro-architecture specification and documentation.
Strong communication skills and the ability to work cross-functionally.
Self-driven, detail-oriented, capable of owning complex design challenges
Fluent in English, both verbal and written.

Advantages:
Experience with high-speed SERDES or parallel interfaces (PCIe, Aurora, Ethernet PHYs, custom links, etc.).
Background in high-speed ASIC design, timing closure at high frequencies, and complex synchronization schemes across clock domains.
Familiarity with verification methodologies (UVM), simulation flows, and coverage-driven verification.
Experience with scripting languages (Python, Perl, Tcl).

Requirements:
What we need to see:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in VLSI CAD tool development, with a strong focus on integrating AI/ML techniques into EDA workflows.
Proficiency in Python and at least one AI/ML framework (such as TensorFlow, PyTorch, or scikit-learn).
Hands-on experience with VLSI physical design and familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence).
Knowledge of data preprocessing, feature engineering, and model deployment as applied to VLSI design challenges.
Experience developing and maintaining automation scripts (Python, Perl, Tcl, Make).
Strong analytical skills in evaluating the impact of AI solutions on design quality, performance, and productivity.
Excellent communication skills and the ability to work cross-functionally in a fast-paced environment.
Self-motivation, attention to detail, and a track record of delivering robust solutions to production.

Ways to stand out from the crowd:
Demonstrated experience deploying AI/ML models in production VLSI CAD environments.
Contributions to open-source AI/EDA projects or publications in relevant conferences/journals.
Deep understanding of VLSI design challenges-such as timing closure, power optimization, or yield enhancement-and how AI can address them.
Experience with cloud-based or distributed compute environments for large-scale AI training and inference.
Strong ownership, curiosity, and a passion for continuous learning and innovation.