דרושים » הנדסה » Analog Layout Engineer

our company's Analog Layout design team is looking for a Senior Analog Layout Design Engineer someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. our company has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.
What you'll be doing:
Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools
You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us.

We are looking for talented and ambitious individuals to join our Hardware team.

Roles and responsibilities:
Definition, design, and production of Chain Reaction reference designs and internal prototyping and evaluation HW.
Product specifications.
Electrical schematics.
Component selection.
Layout guidance.
Hands-on development and testing in a lab environment.
Accompanying production and qualification processes.

our company's Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. our company'sIC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our company's products.
What you'll be doing:
As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.
Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
Optimize package pin out incorporating system level trade-offs of pins assignment.
Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
In close co-operation with the SI/PI/HW design teams and product teams
Planning, ensuring stakeholder management and leading projects from start to finish.

We are looking for Physical Design Engineer.

Roles and responsibilities:
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

our company Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of sectors including high performance computing, enterprise, data centers, cloud computing, and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry. Our product line is focused on delivering the most optimized Ethernet solutions for industries like Media and Entertainment as well as any other industry that can benefit from our DataStream and TCP/IP acceleration.
What You'll be Doing:
Working closely with board design engineers, you'll perform PCB layout of high-speed/high-density value-conscious PCBs for the product engineering unit at our company, using Cadence PCB design tools Allegro 22.1 and Capture
Your focus will be on the complete development of PCB layout, floor planning and detailed component placement, and constraint management, with a concept of topology and signal/trace integrity
Be responsible for the design releases required generation of artwork files, ODB++, test reports, and electronic PCB documentation
The designs you create will need to follow SI constraints
Response on PCB manufacturer EQ/TQ
Review Gerber/ODB++ files
Creating PCB footprint.

Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company's System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.

our company Networking IC Product Engineering team is looking for a System Electrical Characterization and Validation engineer, to take part of Networking system validation and characterization efforts of different platforms and products. You will be a part of a team working on groundbreaking technology. We are in need of hardworking and motivated engineers ready to define and lead validation activities. Do you have analog approach, have passion for lab work, data analysis and post-Si hands on problem solving? We will be happy to have you on our team!
We are looking for a skilled and experienced Engineer with a focus on System Electrical Validation to join our Engineering team in Yokneam, Israel. As part of this role, you will play a crucial role in ensuring the quality of our advanced products. You will collaborate closely with PHY design, system architecture and company wide system, validation, reliability, signal integrity and testing owners to devise and implement effective validation strategies, aligning with our high-quality standards.
What youll be doing:
Create and implement electrical validation plans for new products.
Analyze and interpret validation results to identify potential issues.
Collaborate with design and architecture teams to define required validation and optimize and solve electrical issues.
Design and develop test scripts and frameworks to automate validation processes.
Work closely with software and firmware teams to ensure seamless integration.
Provide technical expertise and guidance to junior team members.
Maintain accurate documentation of validation activities and results.

Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
At our company Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet Layout owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
What you'll be doing:
Be part of a cross-business-unit team and own the high-speed IP integration.
Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
Define and implement efficient, high-quality Full Chip/Chiplet physical design tools, flows, and methodologies.
Gain hands-on experience implementing the partition-level BE design (RTL2GDS).