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You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

You'll be joining our Physical Design team which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Static Timing Analysis, Design Floor Planning, Physical Verification.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Join the team and be part of the cutting-edge innovation that drives our next-generation network devices.
Our unique team operates in a startup-like atmosphere within a stable and leading corporation, working on some of the most advanced silicon technologies. Our design center is home to all silicon hardware and software development disciplines, creating an environment that fosters collaboration and technical excellence.
We are redefining the industry and building the next-generation internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation for all of future routing products. we deliver high-speed networking while ensuring programmability, power efficiency, and scalability across a range of service provider and web-scale markets.
Your Impact:
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

Youll be joining the post silicon validation team in PHY system group Silicon One group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

You'll join our architecture team, central to silicon development .
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specificaton.