דרושים » הנדסה » Senior RTL Designer, Networking

Senior RTL Integration Engineer Networking A unique opportunity to take part in building an R&D team for a global company.

We are seeking highly experienced top talents and visionary hardware designers to contribute to the development of advanced AI connectivity architectures and shape. Responsibilities:
Lead the integration of complex RTL blocks and IPs into large-scale SoCs for AI cloud systems and data centers.
Own and maintain the Front-End environment, integration TFM and data bases
Define and implement chip- and subsystem-level integration architecture from concept to production.
Perform RTL quality checks (Lint, CDC/RDC, power-aware verification, synthesis readiness).
Drive integration flows for clock, reset, power domains, and interconnect fabrics.
Collaborate with cross-functional teams including architecture, RTL design, verification, physical design, DFT, and software.
Contribute to the design of highly innovative Switch and NIC products by ensuring seamless RTL integration.
Act as a key contributor in shaping the integration methodologies and infrastructure of the new Israeli site.

The Senior Manufacturing Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
we are the data platform company for the AI era. We are building the enterprise software infrastructure to capture, catalog, refine, enrich, and protect massive datasets and make them available for real-time data analysis and AI training and inference. Designed from the ground up to make AI simple to deploy and manage, our company takes the cost and complexity out of deploying enterprise and AI infrastructure across data center, edge, and cloud.
Our success has been built through intense innovation, a customer-first mentality and a team of fearless company ronauts who leverage their skills & experiences to make real market impact. This is an opportunity to be a key contributor at a pivotal time in our companys growth and at a pivotal point in computing history.
Role and Responsibilities:
Test Development & Validation
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI)
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. our companys next-generation Ethernet and NVL switches are at the core of the worlds most advanced compute clusters from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at our company, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.
What You'll Be Doing:
Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle from early concept to deployment.
Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
Lead research and exploration of future architectures, including innovation that contributes to patent development.
Collaborate closely with cross-functional teams including other architecture groups, logic design, firmware, system software, and research to ensure successful execution and integration.
Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.

Required Senior uArch Design Engineer
Tel Aviv Israel
A global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

we are seeking an experienced and highly motivated Firmware Engineer to join our NIC/Switch Firmware Development Team in Tel Aviv.
The successful candidate will design and develop innovative firmware features to unleash the full potential of our companys ConnectX/Switch architecture.
Our Firmware Team develops cutting-edge networking features for cloud, HPC, and storage.
This position requires a broad background in NIC or Switch architecture, along with a proven ability to develop robust and efficient solutions to complex design challenges.
The Firmware Team drives the data growth of the worlds largest companies. With talented engineers around the globe, our work environment is dynamic and meaningful.
What You Will Be Doing:
Deepen Your Expertise: Gain a thorough understanding of system debugging, networking technology and stacks, as well as the HW/FW/SW relationships.
Innovate Firmware Features: Design and implement new firmware features in our company's NIC/Switch Firmware core (e.g., our companys ConnectX/Spectrum products).
Optimize Performance: Characterize and refine key firmware design elements and code to maximize performance and ensure robustness and flexibility.
Learn Complex Project Management: Understand how a large, complex software project is operated, maintained, qualified, and released, and learn how hardware and firmware are developed.

We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. our companys next-generation Ethernet and NVL switches are at the core of the worlds most advanced compute clusters from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at our company, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.
What You'll Be Doing:
Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle from early concept to deployment.
Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
Lead research and exploration of future architectures, including innovation that contributes to patent development.
Collaborate closely with cross-functional teams including other architecture groups, logic design, firmware, system software, and research to ensure successful execution and integration.
Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.

our copmpany's Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our company Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

We are now looking for a Principal Formal Verification Engineer to join our our company Networking team!
As a Principal Formal Verification Engineer in our companys Networking Business Unit, you will play a critical role in shaping the formal strategy and execution of complex, high-performance silicon designs that power data centers, AI infrastructure, networking, and storage systems. This is a senior technical leadership role, requiring deep hands-on experience and a strong execution mindset.
You will join a passionate and expert team responsible for applying formal methods to validate designs at the highest level of rigor. This role offers the opportunity to work at the cutting edge of formal verification, influence architecture, and collaborate across functions to drive best-in-class silicon quality.
What Youll Be Doing:
Define and execute advanced formal verification strategies for complex digital blocks and systems.
Lead formal activities across multiple projects, ensuring scalability, completeness, and convergence .
Guide the development of formal testbenches, properties, assertions, and coverage models.
Collaborate with architects, RTL designers, and DV teams to identify formal targets and maximize design verification efficiency.
Provide technical leadership and mentoring to other formal engineers and contribute to the growth of formal expertise within the organization.
Evaluate and deploy state-of-the-art formal tools, flows, and methodologies to continuously improve formal verification coverage and impact.

Join our innovative Mixed-Signal Design group as a SerDes/PHY Micro Architect, and help shape the future of high-speed silicon for next-generation networking and GPU's ASICs. In this strategic role, you will define and refine system-level features and micro-architecture requirements for advanced SerDes and PHY IP, with a special focus on firmware (FW) architecture and CD architecture integration.
You will be involved end-to-endfrom early requirements through pre-silicon architecture to post-silicon bring-up and customer-facing debugcollaborating closely with design, verification, firmware, hardware, and system teams. Your work will enable cutting-edge technologies such as CPO and NVLink.
What Youll Be Doing:
Define system-level features and micro-architecture requirements for SerDes technology, bridging hardware and firmware domains.
Align architecture definitions with both FW development and CD implementation flows, ensuring seamless integration across product stages.
Translate system and customer requirements into scalable, actionable features for next-generation silicon.
Drive and contribute to all silicon development phases: pre-silicon specification, hands-on lab bring-up, validation, debug, and customer support.
Collaborate with cross-functional teams across ASIC design, verification, firmware, board engineering, and customer delivery.
Lead or contribute to technical reviews, issue root-cause analysis, and architectural methodology improvements.

We are now looking for a Formal Verification Manager to join our company Networking team!
As a Formal Verification Manager in our companys Networking Business Unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of our companys cutting-edge Network products and GPU technologies.
This is a unique opportunity to make a real impact at the heart of our companys AI and HPC revolution, while working in a fast-paced, innovative environment.
You will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.
What Youll Be Doing:
Lead and grow a team of formal verification engineers focused on pre-silicon Formal verification of complex digital designs.
Define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.
Provide technical guidance, mentoring, and support to engineers in the team.
Own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.