דרושים » חומרה » Senior Chip Architect, Next Gen Networking

We are seeking a highly motivated Chip Design Architect to join our team of experts and help shape the future of high-performance computing. Our next-generation Infiniband and NVL switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in industries such as finance and research labs. As a Chip Design Architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation of switches that will be used by top researchers and engineers around the world. The products you'll develop will be integrated in many leading-edge compute clusters, and supercomputers, and you'll be part of a team with a strong track record of success.
What you will be doing:
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project.
Define the HW boot, clock and Reset architecture for Switch ASIC
Develop slow-speed interface architecture specifications and design guidelines, conduct trade-off analysis for different architecture options, and oversee the implementation of the chosen architecture by the chip design / FW / SW teams.

Our technology has no boundaries! we are building the worlds most groundbreaking and state of the art accelerated compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers.
We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect at our company, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Developing models for simulations and performance testing, analysing the results and development of future HW and SW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our companys next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.
What you'll be doing:
Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.
Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
Define the implementation of debug capabilities to support performance validation and improvements
Understand our system requirement and help define the POR of our switch product line.
Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

Join our company and Shape the Future of AI Infrastructure.
At our company, our inventions are the engine of accelerated computing and modern AI. Our work powers everything from groundbreaking scientific research to the generative AI applications transforming our world. We believe that our people are our greatest strength, and we're looking for a skilled PCIe Firmware Engineer to join our team and help our customers succeed.
In this role, you will be a critical link between our pear team / QA / Application and the PCIe FW design team. You will have a direct impact on our business and technology by solving sophisticated technical challenges and ensuring our customers can build the next generation of supercomputers and AI fabrics.
What you will be doing:
Solve complex problems: Investigate, debug, and resolve challenging PCIe firmware issues for our most important customers, serving as their trusted technical expert.
Collaborate across teams: Partner with our Chip Design, Software, and Architecture engineers to find root causes and develop robust, long-term solutions.
Influence product development: Translate customer needs and field data into actionable feedback that directly shapes the future of our products.
Share your knowledge: Help improve our team's processes and contribute to our knowledge base, making everyone more effective.

Our technology has no boundaries! we are building the worlds most groundbreaking and state of the art accelerated compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers.
We are seeking a highly motivated architect to join our team of experts and take part in shaping the future of high-performance and ML / AI computing. Our next-generation InfiniBand and NVLink systems will be at the heart of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today. As a system/software architect at our company, you will have the opportunity to work on some of the most innovative technology that is currently driving the world forward.
What youll be doing:
Define the next generations of our company's communication SW architecture.
Research of various solutions by defining and running POCs, evaluate SW and HW impact and conveying the solution architecture to the relevant teams. The solutions can span over various layers: from algorithms and high level software to firmware and HW.
Collaborate with multi-functional teams, including other architecture teams, VLSI logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

we are seeking a highly motivated and experienced System Test Architect to define, develop, and drive comprehensive validation strategies for next-generation hardware platforms. As a key member of our hardware architecture and systems engineering team, you will be responsible for ensuring the robustness, performance, and scalability of our company's cutting-edge products across AI, graphics, data center, and automotive domains. You will collaborate with cross-functional teamsincluding silicon design, board design, firmware, and software engineeringto create innovative test methodologies that validate complex system-level interactions. Your insights and expertise will directly impact product quality, development efficiency, and time-to-market.
What you will be doing:
Architect end-to-end system validation strategies for new hardware platforms.
Define test coverage and validation methodologies.
Collaborate with hardware, software, Qual and QA teams to align on product requirements and test coverage plans.
Lead development of automation frameworks and diagnostics tools to enable scalable and repeatable testing.
Analyze test data to identify root causes, guide debug efforts, and improve validation coverage.
Provide technical leadership and mentorship across multidisciplinary teams and represent system test considerations in architecture and design reviews.

we are widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
we are looking for a phenomenal Senior Verification Engineer for HW Simulation for the ChipSim Group. You will join the ChipSim growing team and take our product to next level, working closely with HW design and architect teams and gaining a deep understanding of our companys products and technologies.
What Youll Be Doing:
Develop and maintain robust test environments, verification flows, and infrastructure.
Define and execute comprehensive test plans for existing and next-generation networking features.
Take ownership of functional, integration, and regression testingfrom planning through execution.
Build automated test suites and integrate them into CI pipelines to ensure quality at scale.
Collaborate across architecture, firmware, and HW teams to drive quality and early bug detection.
Analyze complex system behaviors and drive debugging efforts across hardware and software boundaries.

Join our innovative Mixed-Signal Design group as a SerDes/PHY Micro Architect, and help shape the future of high-speed silicon for next-generation networking and GPU's ASICs. In this strategic role, you will define and refine system-level features and micro-architecture requirements for advanced SerDes and PHY IP, with a special focus on firmware (FW) architecture and CD architecture integration.
You will be involved end-to-endfrom early requirements through pre-silicon architecture to post-silicon bring-up and customer-facing debugcollaborating closely with design, verification, firmware, hardware, and system teams. Your work will enable cutting-edge technologies such as CPO and NVLink.
What Youll Be Doing:
Define system-level features and micro-architecture requirements for SerDes technology, bridging hardware and firmware domains.
Align architecture definitions with both FW development and CD implementation flows, ensuring seamless integration across product stages.
Translate system and customer requirements into scalable, actionable features for next-generation silicon.
Drive and contribute to all silicon development phases: pre-silicon specification, hands-on lab bring-up, validation, debug, and customer support.
Collaborate with cross-functional teams across ASIC design, verification, firmware, board engineering, and customer delivery.
Lead or contribute to technical reviews, issue root-cause analysis, and architectural methodology improvements.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join our team as a Senior Power and Performance Architect - Networking, influencing the future of network systems at our company.
What you'll be doing:
Develop, model, and validate groundbreaking power and performance optimization techniques for network fabrics, components (NICs, Switches), and systems. Collaborate closely with cross-functional teams including silicon design, system architects, software/firmware engineers, performance analysts, thermal engineers, and AI researchers to ensure end-to-end power and performance optimization. You will determine strategies that successfully implement flawless performance and power efficiency in our ambitious projects!

we are seeking a sharp, innovative, and hands-on Architect to help shape the future of LLM inference at scale. Join our dynamic E2E Architecture group, where we build cutting-edge systems powering the next generation of generative AI workloads. In this role, you will work across software and hardware domains to design and optimize inference infrastructure for large language models running on some of the most advanced GPU clusters in the world.
Youll help define how AI models are deployed and scaled in production, driving decisions on everything from memory orchestration and compute scheduling to inter-node communication and system-level optimizations. This is an opportunity to work with top engineers, researchers, and partners across our company and leave a mark on the way generative AI reaches real-world applications.
What Youll Be Doing:
Design and evolve scalable architectures for multi-node LLM inference across GPU clusters.
Develop infrastructure to optimize latency, throughput, and cost-efficiency of serving large models in production.
Collaborate with model, systems, compiler, and networking teams to ensure holistic, high-performance solutions.
Prototype novel approaches to KV cache handling, tensor/pipeline parallel execution, and dynamic batching.
Evaluate and integrate new software and hardware technologies relevant to model inference (e.g., memory hierarchy, network topology, modern inference architectures).
Work closely with internal teams and external partners to translate high-level architecture into reliable, high-performance systems.
Author design documents, internal specs, and technical blog posts and contribute to open-source efforts when appropriate.