דרושים » הנדסה » Verification Engineer

We are seeking a highly skilled and expert Verification Lead to join our PCIe Firmware team. In this role, you will be responsible for supervising the verification plans, monitoring their execution within the teams, guiding engineers through the verification implementation, and tracking coverage, Coverity, and other relevant statistics. You will be joining a team dedicated to developing groundbreaking technology and building the core technology of next-generation our devices across various fields, including low-level C layer between hardware and firmware, C++ verification environment, automation challenges, and Python testing environment.

What youll be doing:

Develop and lead verification plans, ensuring they are driven effectively within the teams.

Provide guidance to engineers on verification implementation within the verification environment.

Monitor coverage, Coverity, and other statistics to ensure comprehensive verification and optimization of next-generation our products.

Work closely with firmware design, chip design, software, and architecture teams to define and craft both legacy and new low-level firmware flows.

Enhance methodologies and automated processes to improve efficiency and effectiveness.

We are now looking for a Senior Chip Design Verification Engineer to join our Switch Silicon team.As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a design/verification team which develops core units within the Switch silicon.

Micro-architecture of dynamic verification environments planning for units and modules.

Design dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are now looking for a best-in-class Senior Chip Design Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer in our GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry our GPU Super-Chip.

What youll be doing:

Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU.

Integrations and Full-Chip models.

Verification of chip blocks/entities according to specifications under challenging constraints.

Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration.

We are seeking a top SOC Verification Engineer to verify the design and implementation of the worlds leading networking SoCs. In this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. This is your chance to shape the future of computing with a world-class team!

What you'll be doing:
As a Verification Engineer, you will be responsible for verifying design, architecture, and micro-architecture using advanced verification methodologies.

Define the verification scope and contribute to the development of the verification infrastructure for SOC clock networks.

Verify firmware code, with a specific focus on hardware/firmware interactions.

We are looking to hire a Chip Design Verification Engineer to join our Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, and Verification. Work with the best and become one of the best!

What you will be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join Beer-Sheva/Tel-Aviv group, working on verification in the field of encryption accelerators.
Verification for chip blocks/entities/IPs according to specifications under challenging constraints and with high orientation to power & performance and modular, reusable and parametric designs.
Daily work will involve verification and might involve any or all aspects of chip development including design and micro-architecture.
Work closely with firmware and other groups around the globe.
Work mode: Hybrid home-office

Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, DV, ARCH and multiple production teams.
Provide quality functional coverage for Google designs.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join Beer-Sheva/Tel-Aviv group, working on verification/design in the field of encryption accelerators.

Verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work will involve verification and might involve any or all aspects of chip development including design and micro-architecture.

Work closely with firmware and other groups around the globe.

Work mode: Hybrid home-office.

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

VLSI group is responsible for the development of our next generation SoC for AI Compute. The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.

We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.