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We are looking for a Hardware failure analysis engineer to join the Interconnect FA team. This position will be part of the product engineering team which control our Interconnect production lines. The ideal candidate will roll out failure analysis of products, while reviewing both the design and hardware assembly while executing manual and automated tests.

What you'll be doing:

Review architectural design (electrical, mechanical, process, software) of the tested units to locate potential design issues.

Design, develop and execute test suits to find the root cause for the HW malfunction of customers returned or production material.

Connect with inner / external customers for background review.

Finalize the investigation to summary reports.

We are looking for a Test Development Engineer to join our team. This role will work as part of a team driven by the development of our networking and interconnect products. Do you have a passion for automation development, test program development, code writing and looking for sophisticated and significant topics? We will be happy to have your skills on the team. You will handle various projects across teams, build test plans, automate test specification and execution. You will continuously innovate and develop scalable, reliable, high-performance systems and tools to enable the next generation of Interconnect products.

What Youll Be Doing:

Will work on projects across multiple functional teams from different geographies throughout the product lifecycle.

Develop test plans, execute testing via automation and/or manually for all supported hardware releases.

Work with cross-functional teams across engineering, thermal, mechanical and HW to identify test requirements.

Develop automation and tools for our hardware releases and test environment.

Debug of HW & SW failures in interconnect product, Isolate the problem and get to the root cause.

Design and build technical processes to address business issues.

Deploy the test solution to the production sites and provide support if needed.

Train personnel on the required processes and operations of complex test systems.

We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Act as Partition/Unit level physical design technical leader and focal point.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies, and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be part of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

We are seeking a Build Project Manager who is passionate about working on products that enable deep learning. Our team manages the NPI networking supply chain for engineering activities. Activities start from very early engagement with design engineering team and follow through all quick turn NPI builds at the shortest possible cycle time. Our team supports all these engineering quick turn activities by engaging with the engineering team, material suppliers, Operations team, and the PCB manufacturing team. All the parties need to be kept aligned while engineering keeps changing either the material sets or the process.

We are looking for someone can work in a dynamic and fast-changing environment. You are someone who enjoys working on groundbreaking technology and enjoy working with people to take on problems. As a Build Project Manager, you are able to see both the high-level view and be proficient in tracking and following up on detail whether it is an existing product that requires new qualifications or a ground up new product. We will expect you to understand technical detail and be able to translate that into program impact.

What you'll be doing:

Build and track project details.

Communicate with other team members and suppliers to get project details.

Flexibility to adapt to changing requirements, diverse project needs, and tight timelines.

Ability to report on program details in Alignment meetings.

Track and communicate key deliverables, constraints, risks, dependencies and clearly identify critical paths while working with ASIC, product, test, software, board, system engineering and planning teams and other program managers towards a common goal.

Manage cross-functional communications independently, work within a matrixed and publish progress/roadblocks and highlight risks to upper management.

Bring diverse and globally distributed teams together to tackle complex problems and work towards closure.

Lead and attend cross-functional NPI meetings related to your product and highlight key Ops issues while ensuring that the product is ready for production.

Be an active participant in the NPI team by recommending methodology improvements that we can practice as a team.

We are now looking for a Chip Design Student for the NVIDIA SOC team.

As a Chip Design Student at NVIDIA, you'll join a group of passionate engineers and students to design and implement the next generation state of the art DPU SOC chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency.

What you'll be doing:

Work in a combined design and verification team which develops some of the SOC silicon core units

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.

Partner closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are searching for PCB layout manager to expand Networking HW Group. As a PCB Layout manager at NVIDIA, you will design and development of complex printed circuit boards (PCBs) for networking hardware products. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines that empower most advanced data canters in the world. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you'll be doing:

Lead and manage a team of PCB layout engineers within the Networking HW Group.

Collaborate with cross-functional teams including hardware design, validation, and manufacturing to ensure successful project delivery.

Define and implement best practices for PCB layout design, ensuring high-speed signal integrity and manufacturability.

Provide technical guidance and mentorship to team members, fostering their professional growth and development.

Coordinate with external vendors and PCB fabrication partners to support project requirements.

Participate in strategic planning and roadmap discussions to support the long-term goals of the Networking HW Group.

Coordinate resources and collaborate with other PCB layout teams at Nvidia worldwide to leverage expertise and ensure alignment on projects.

We are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Leading and mentoring Physical Design-Backend team.

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for a talented Senior HPC and AI Networking Performance Research and Analysis Engineer to join our Performance group.

The ideal candidate will profile and analyze AI workloads on large GPUs and CPUs scale clusters for distributed Deep Learning LLM training focusing at the collectives communication and networking.

You will work and interact with many types of HW and platforms such as HCAs, Switches, CPUs, GPUs, and Systems.

You will experience with and develop performance analysis tools and methodologies to dive deeply into the details, understand performance expectation, limitations, and bottlenecks.

What you'll be doing:

Experience and research AI workloads and DL models specifically tailored for large-scale deep learning LLM training on our supercomputers with a focus on High-performance networking.

Benchmarking, Profiling, and Analyzing the performance to find bottlenecks and identify areas of improvement and optimizations, with a strong emphasis on networking aspects.

Implement performance analysis tools.

Collaborating with many teams from HW to SW to provide performance analysis insights.

Define performance test planning , set performance expectations for new technologies and solutions, and work to reach the performance targets limits.