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We are looking for a motivated and curious student to support our infrastructure and automation efforts. Youll help develop testing tools, integrate lab test equipment, and explore AI-based insights for smarter test analysis.
You'll be exposed to advanced lab setups, real-time testing systems, and tools that support product release decisions, all while being part of a high-performance engineering culture.
This is an ideal role for a student studying engineering or computer science, eager to gain real-world experience in system validation and automation.
Roles and responsibilities:
Design, develop, and maintain automated test infrastructure.
Develop tools to simulate, validate, and verify complex hardware/software systems.
Develop software interfaces to control and monitor test equipment (e.g., oscilloscopes, power supplies, signal generators, protocol analyzers).
Integrate AI/ML models for test optimization, log analysis, anomaly detection, root cause identification, and system insight.
Create dashboards, reports, and intelligent insights from test data and logs.

EDA/CAD Software Engineer
About The Position
The company designs and builds hardware that fuels advanced privacy technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure cloud computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data-analysis and real-time computing is acceleration - existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us.
Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.
Roles and responsibilities
Build, maintain, and optimize CAD tools supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate design flows spanning frontend RTL-to-GDSII, digital backend implementation, and physical/verification signoff, ensuring scalability and tapeout readiness.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Design and implement testing frameworks, regression suites, code review practices, and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

Required Senior VLSI Backend Engineer
We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

We are in the early stages of a new project and looking for a talented Senior engineer to take on a key role, leading Verification efforts of major parts of our ASIC - from scratch
Roles and responsibilities
Take ownership of Verification for large ASIC clusters.
Plan, build, and execute the Verification environment end-to-end.
Mentor and guide juniors/students.