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We at our company are passionate believers in the value and power of 3D printing, and in the change it can bring to design, innovation and manufacturing. The solutions we create are used by over 20,000 enterprises worldwide, and are rapidly changing the way products are imagined, designed, marketed, produced, supplied and sold. We are literally shaping the world that surrounds us - from the products and services in our lives and homes, to our health and quality of life, our transport, security and economies, to how we teach, research and even learn.
we are the largest 3D printing solutions company in the world - a company at the forefront of 3D printing innovation for more than 25 years
In this role you will:
Serve as the Finance business partner to support Business units:
Serve as the business partner for multiple technologies leaders.
Responsible for budget management and analysis throughout the AOP, quarterly forecasts and actuals.
Take an active role in strategic and road map processes including building 5-years models, to support financial planning and strategic decisions making.
Participate in the Product Life Cycle process implementing business plans for new/ existing products, analyze and evaluate projects (including ROI and go/no go analysis) and support financial issues within the process.
Participate in financial improvement plans to meet quarterly/annual objectives.

we are looking for a strategic and analytical Senior Compensation & Benefits Partner to lead Total Rewards across EMEA & APAC.
In this role, you will design, implement, and manage competitive and compliant compensation and benefits programs, while partnering closely with regional leaders and the global Total Rewards team. Youll balance global consistency with local market expertise and play a key role in shaping our employee value proposition across diverse markets.
What Youll Do
Compensation Leadership
Lead regional merit, bonus, equity, and promotion cycles
Provide guidance on hiring, mobility, promotions, and retention
Conduct market pricing and compensation modeling
Partner on job architecture and leveling frameworks
Ensure compliance with pay transparency and labor regulations
Benefits Strategy & Management
Oversee health, retirement, wellness, and insurance programs across EMEA & APAC
Lead renewals and vendor partnerships
Support global harmonization while respecting local requirements
Governance & Compliance
Ensure compliance with local labor and tax regulations
Maintain documentation, controls, and audit readiness
Monitor regulatory changes and assess program impact
Business Partnership
Serve as the primary Total Rewards partner for HR and business leaders in the region
Translate complex compensation topics into clear guidance
Support manager enablement and employee education
M&A & Integration
Support compensation and benefits due diligence for mergers and acquisitions
Lead Total Rewards integration planning and post-merger harmonization (PMI).

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we are leading the global shift to additive manufacturing with innovative 3D printing solutions for industries such as aerospace, automotive, consumer products and healthcare. Through smart and connected 3D printers, polymer materials, a software ecosystem, and parts on demand, our company solutions deliver competitive advantages at every stage in the product value chain. The worlds leading organizations turn to our company to transform product design, bring agility to manufacturing and supply chains, and improve patient care.
As part of this role you will:
Provide on‑line engineering support and resolve mechanical/technical issues fast.
Improve yield, cycle time, labor efficiency, and overall production performance.
Maintain and optimize work instructions, documentation, tooling, and fixtures.
Support NPIs/EOL and collaborate with cross‑functional teams, subcontractors, and partners.
Reduce rework and scrap and lead second‑source qualifications to strengthen quality and supply resilience.

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.


Key Responsibilities

Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis     

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

End-to-End Sourcing Management
Lead the full sourcing lifecycle for assigned indirect categories, including market analysis, supplier selection, competitive bidding, and negotiations.
Ensure sourcing activities support cost optimization, quality, and compliance, in line with company policies, approval processes, and documentation standards.
Supplier & Contract Management
Build and maintain strong relationships with key suppliers to ensure service continuity, risk mitigation, and ongoing value creation.
Manage contract execution, track supplier performance (KPIs), and ensure all agreements and documentation are properly maintained.
Cross-Functional Collaboration
Partner closely with internal stakeholders to understand business needs and translate them into effective sourcing strategies.
Provide guidance on procurement processes, ensure adherence to sourcing standards, and support internal customers throughout the procurement lifecycle.

we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

As a Principal/ Senior Principal ASIC Architect, you will be the blueprint creator for the future of AI infrastructure. You won't just follow specifications-you will lead the definition and execution of next-generation ASIC solutions targeting hyperscale data centers. From analyzing market requirements to guiding products through their entire lifecycle, your influence will be etched into the silicon that enables the next era of scale-up and scale-out connectivity. If you thrive on solving complex, unnamed challenges and want to shape the architectural foundation of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Architectural Definition & Strategy

Lead the architectural definition of next-generation ASICs, translating complex market requirements into elegant, high-performance hardware specifications
Drive technical decision-making that balances power, performance, area, and cost (PPAC) to maintain competitive edge in the hyperscale ecosystem
Leverage deep domain expertise to integrate industry standards (Ethernet, UALink, PCIe) into cohesive systems solving demanding AI infrastructure challenges
Product Lifecycle Ownership

Own the architectural journey from initial concept through design, implementation, tapeout, and mass production
Ensure final products deliver on performance promises and meet hyperscaler requirements
Drive architectural exploration and performance modeling to validate design decisions
Technical Leadership & Cross-Functional Collaboration

Act as the technical North Star for the engineering organization in Israel
Collaborate across Architecture, Design, Verification, DFT, and Backend teams to ensure seamless execution
Influence and align cross-functional teams around unified technical vision through strong communication and leadership