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Required PHY Firmware Technical Leader
Meet the Team:
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices.

we are looking for an experienced Data Center Operations Engineer to join our IT department. In this role, you will maintain and support a large-scale global server and GPU infrastructure, monitor and troubleshoot hardware failures, and collaborate with senior system specialists to resolve complex issues across production and research environments.
We offer a dynamic, innovative production and research environment and expect a strong commitment to maintaining high service availability, performance, and reliability.
Responsibilities :
Deploy (rack and cable) new servers, GPUs, and infrastructure hardware.
Monitor and troubleshoot IT infrastructure hardware issues across all company data centers.
Coordinate vendor engineers site visits.
Perform hardware break/fix activities including replacement of drives, RAM, CPUs, GPUs, power supplies, and other server components.
Maintain firmware versions up to date.
Manage company data center inventory.
Monitor and manage DC environment parameters including power usage, airflow, cooling, and rack capacity.
Support and keep hardware in an high-performance compute environments used for compute-intensive workloads and research activities.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.
Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority - bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges.
You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data.
Responsibilities:
Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments
Define and drive architectural solutions - not only identify problems, but come with concrete proposals and alternatives
Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack
Analyze bottlenecks and performance on workloads reflecting future AI use cases
Provide proof-of-concept implementations for new architectural features and design alternatives
Potentially lead feature definition in addition to the modeling role

we are looking for a Compilation Technology Expert.
This team will operate under a unique manner, as described below -
The environment
- Startup-like intensity
Small team
High ownership
High visibility
Merit is the essence, not titles
- Fast pace
Todays state of the art is tomorrows baseline
We aim to go beyond
- Incubator mindset
Take on hard challenges, dismantle, and regroup as novelty
- Elite technical culture
Strong experts
Strong standards
Strong execution.
Ratio beats seniority, not the other way around
- No artificial boundaries
We challenge assumptions, and question constraints, and leave no quarter
- Direct exposure to the latest and greatest AI technology
Real hardware
Real toolchains
Real large-scale AI applications
All pass through and impacted by our work
- First-principles thinking
out-of-the-box is a compromise
Do not accept that a box had to exist in the first place.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovative chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join the Tel Aviv or Beer-Sheva group, working on RiscV processors platform.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development including verification, integration, debug

Work closely with firmware and other groups around the globe.

We are looking for a passionate and experienced software developer to join our Chip Design Technologies group, helping to build the tools that shape the future of Chip Design and Verification. This role is at the intersection of software engineering and hardware design. Youll work on the software that accelerates the development of our industry-leading networking chips - highway for the AI revolution.

We're looking for someone who combines strong coding skills with preferably a solid understanding of chip design or verification. If youre excited about solving technical bottlenecks, building scalable tools, and collaborating with designers and verification experts, youll feel right at home here.

What youll be doing:

Develop software tools for our chip design and verification flows

Collaborate closely with designers and verification engineers to identify bottlenecks, propose improvements, and build software solutions that boost productivity and quality.

Own your solutions end-to-end - from idea to delivery to support.

We are looking for a Formal Verification Engineer for our NVIDIA Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our Switch team delivers world class Bridge and router solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

We are looking for a Chip Design Manager to join our Networking team! As a Chip Design Manager in our Networking Business Unit, you will lead a team of highly skilled engineers responsible for verifying the next generation of our cutting-edge network products and GPU technologies. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will join a passionate, experienced team working at the forefront of silicon verification - using advanced methodologies and tools to ensure design correctness for world-class solutions in data centers, high-performance computing, networking, and storage.

What You'll Be Doing:

Lead and grow a team of formal verification engineers focused on pre-silicon FV of complex digital designs.

Define and drive strategies and methodologies across multiple projects to prove design correctness and ensure quality.

Collaborate closely with Architecture, Design, and DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers on the team.

Own planning and execution of verification deliverables to ensure high quality and timely tapeouts.

We are seeking an AI Networking Exploration Architect for our Networking Insights Group to bridge the gap between cutting-edge, hyper-scale AI workloads and the datacenter infrastructure that enables them. You will join a small, focused team of multidisciplinary engineers driving AI workload optimization through deep application understanding and end-to-end systems thinking. Your insights will directly shape our products across the full stack-from applications and software libraries to hardware architecture and physical design.

What You'll Be Doing:

Model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations.

Translate state-of-the-art research into actionable infrastructure, software, and hardware features in partnership with architecture teams.

Rapidly master new AI domains (LLMs, generative models, multimodal systems) and distill key findings for product teams.

Incorporate your deep knowledge of AI applications into our hardware and software roadmaps.

Conduct independent research by formulating hypotheses about workload behavior and validating them through rigorous analysis.

Drive architectural innovation and network optimization by applying your domain expertise to exploratory analysis of real-world Deep Learning (DL) workloads.

We are looking for a Team Leader to build and run our Customer Facing Architects group focused on Spectrum-X in Israel. This team serves as the technical connection between our internal AI Networking compose group and our top customers. These include hyperscalers, cloud service providers, sovereign AI initiatives, and corporate AI solution developers rs.

What youll be doing:

Team Leadership, Build and guide a team of senior Spectrum-X customer-facing architects. Set technical direction, own hiring and mentoring, and establish clear roadmap for customer early engagement, onboarding and tracking lifecycle.

Customer Architecture & Technical Ownership, Serve as the senior technical authority for Spectrum-X deployments at hyperscalers, national AI programs, and enterprise AI factories. Drive E2E solution adoption, lead sophisticated technical architecture issues in the solution, and guide customers through configuration, tuning, and performance debugging at the NIC, switch, and fabric level. Convey customer's needs, and lead strategic PoCs and benchmarks to demonstrate Spectrum-X advantages.

Product Feedback, Turn field findings and customer difficulties into concrete feedback for R&D, ASIC, and software teams while partnering with AI Networking Architecture to make sure our deployment realities shape next-gen Spectrum-X design.

Work with Product Management to influence reference architectures and go-to-market strategy and represent Spectrum-X at customer briefings and industry events such as SC, OCP, and Hot Interconnects

We are looking for an experienced networking software engineer. An awesome candidate is highly technical who is also comfortable with dealing with enterprise customers. You will join a team of Solution Engineers focused on the Mellanox Networking, DGX Platforms, Container Orchestrators, Deep Learning containers, and other Enterprise related system software.

Solution Engineers spend approximately 50% of their time helping customers with their most complex problems and 50% of their time doing development related work. This individual should have proven grasp of datacenter and networking technologies, to provide comprehensive solutions for complex installations, maintenance, or operations for a broad scope of leading-edge networking products.

What you'll be doing:

Develop features and tools as part of solution engineering efforts to support all Enterprise Service offerings including, but not limited to Networking/switching products.

Work with our Enterprise customers and internal users to improve the availability, reliability, and overall experience of working with our Networking products.

Take ownership and drive customer issues with Ethernet or InfiniBand switch network deployments from inception to resolution.

Bring independent analysis, communication, and problem-solving to customer experience.

Collaborate with engineering to document, recreate and solve issues.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.