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Were expanding our teams and looking for an Experienced Physical Design Engineer who is ready to make a massive impact
NOTE: By applying for this position, you will have the opportunity to indicate your preferred work location: Haifa or Petach Tikva.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Were looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff: on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

We are looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting-edge technologies - Autonomous Vehicle (AV) SoC.
We know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules.
Verify and Validate our design.
Debug and analyze coverage and yield loss.
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

Our Unit Level Verification Team is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

We are looking for a highly experienced a hands-on Compiler Engineer who embodies ambition and positivity.

Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.

Requirements
Responsibilities:

Develop compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
Take on complex optimization challenges at the core of our unique compiler, focusing on real-time applications, hybrid quantum/classical algorithms, and parallel processing.
Conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
Hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
Collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.

We are looking for an excellent design engineer to join our team and build QM's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists

Responsibilities:

Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface

Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.

What You'll Do:

Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team

This position is responsible for supporting daily operations and projects with installation, configuration and maintenance of process control & automation systems including Programmable Logic Controllers (PLCs), Human Machine Interface (HMIs) and SCADA systems.

This position is responsible for interpreting Control Philosophies, Cause & Effects, P&IDs and developing, testing, documenting, and maintaining Rockwell ControlLogix PLC & FactoryTalk HMI based systems and Archestra System Platform object-based programs, templates, processes, and tools to manage and sustain programming code for offshore and high-pressure gas production facilities. Supports project activities including facility design, construction, commissioning, troubleshooting, managing, and maintaining SCADA, DCS, SIS, HMIs, PLCs, PCN Servers & Applications and Communication systems reliability and availability. Maintains SCADA data reporting systems, support Operations production reliability and optimization efforts and support PCN Information Risk Management (IRM) compliance. Train and mentor Operations and Maintenance personnel.

Familiarization with the following software packages preferred:
RSLogix 5000, Studio 5000.
Factory Talk Asset Center.
Factory Talk View ME & Factory Talk View SE.
Archestra System Platform.
Wonderware Intouch.

We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SoC integration.

As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks.



Responsibilities

RTL design and implementation of new IPs
SoC integration and design ownership of chip subsystems
Exploration and evaluation of new protocols and architectural solutions
Close collaboration with architecture, verification, validation, software, and back-end teams
Delivering high-quality, best-in-class RTL that meets performance, power, and area goals

We are seeking a highly skilled Emulation Engineer with extensive experience in the semiconductor industry to join our Chip Design team.

The ideal candidate will have a proven track record working with advanced emulation platforms, particularly Veloce, Palladium or Zebu.

Key Responsibilities:

Develop and maintain emulation models from RTL for complex SoC designs
Port RTL designs into emulation platform
Debug hardware and software issues in pre-silicon environments
Collaborate with frontend design, design verification, validation and software development teams to create comprehensive test strategies
Set up and maintain emulation hardware infrastructure
Develop workflows for efficient emulation processes
Collaborate with emulator vendor field service engineers to resolve hardware issues
Support users and debug issues

abra is seeking a Senior FPGA Engineer This role requires close collaboration with multidisciplinary teams, including hardware, software, verification, and system engineers, to deliver high-performance, mission-critical FPGA solutions—from concept and design through development and production, all the way to integration and operational deployment.

Required Camera System Engineer
About the team:
We build camera-based ADAS and autonomous-driving systems with leading OEMs. This role is part of the Optical Path System Architecture and Integration team: the group that takes a new sensor integration from early requirements to a fully validated optical path.
As Camera System Engineer you will drive the full integration lifecycle of complex real-time embedded systems - bridging hardware platforms and software stacks from early requirements definition and platform bring-up through system-level validation and verification.
You will support pre-nomination and help close optical-path requirement gaps. Working closely with the Camera SW team and providing the pre-requisite they need for development and productization.
What will your job look like?
Define bring-up prerequisites and phases with architecture and program managers.
Support Bring up of optical path devices (Sensor, Serializer, Deserializer).
Review and contribute to Hardware-Software Interface specifications (register maps, memory maps, interrupts, boot sequences)
Support pre-nomination requirement definition, including customer-facing meetings when needed.
Support architecture with optical path feature requirements and sensors bring up requirements.
Support SW/HW integration test strategy including HIL setups and CI automated regression.
Deep co-debugging using Saleae, logic analyzers, and oscilloscopes; root cause analysis across hardware errata, timing, and firmware issues.