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Perform validation tests at product board and system levels, to ensure compliance with specifications, standards and customer requirements.

we are a leading company specializing in the development and manufacturing of autonomous drone systems. Its solutions combine hardware, software, and AI-driven technologies to support complex, large-scale operations. our company works primarily with defense industries, such as military and law enforcement agencies worldwide. The company is part of Ondas Holdings and operates as a wholly owned subsidiary.
We are looking for an system validation manager to lead the companys end-to-end experimental and system-validation activities for complex unmanned and multidisciplinary systems. The role requires a strong engineering leader who can translate system requirements into well-defined experiments, lead hands-on execution, analyze results, and deliver clear engineering conclusions and recommendations.
Responsibilities
Own test and validation activities from requirement understanding through planning, execution, analysis, reporting, and closure.
Work with System Engineering and R&D teams to define test objectives, scenarios, methods, instrumentation, and measurable pass/fail criteria.
Write professional test plans, procedures, readiness checklists, and final test reports with clear traceability to requirements.
Plan and lead laboratory, ground, field, and flight-test campaigns for UAVs, docking stations, payloads, communication systems, and other subsystems.
Ensure full test readiness: system configuration, test equipment, instrumentation, safety, range/logistics, personnel, and data collection.
Lead hands-on test execution, troubleshoot issues in real time, and make sound engineering decisions in dynamic field environments.
Analyze logs, telemetry, measurements, and system behavior; identify failures, trends, root causes, and gaps requiring further investigation.
Drive post-test debriefs, conclusions, lessons learned, corrective actions, and regression/verification activities.
Lead and develop the experiments/test team, establish professional standards, prioritize activities, and continuously improve test methodology.

We are looking for a Verification and Validation Test Engineer to support our companys product development activities through the design and execution of detailed, comprehensive, and well-structured verification tests.
In this role, you will translate product requirements into effective test procedures, develop test strategies and fixtures, execute tests, and document results and anomalies. You will work closely with engineering and quality team members in Israel and Portsmouth, NH, contributing directly to the robust verification of our companys products.
While the role includes testing activities, it is not a software QA position.The focus is on hardware verification and validation, including hands-on test execution and the use of laboratory and test equipment.
This is a full-time, exempt position based in our Haifa office and reports to the Verification and Validation Manager.
What you will do:
Analyze product requirements and develop test procedures based on them.
Plan test strategies and design test procedures using demonstration, measurement, inspection, and analysis techniques.
Ensure efficient and robust coverage of requirements through different test scenarios.
Write instruction-based test procedures and design test fixtures as needed.
Establish clear traceability between requirements and test procedures.
Review test cases created by peers and recommend improvements.
Execute test procedures and document results in test reports.
Identify and report anomalies encountered during test execution.
Collaborate closely with our company engineering team members in support of product development activities.

Our Sat Connect IC business unit, a division of our Satellite Systems business is a leading provider of ASICs, software, multibeam electronically steered antennas, and complete systems for communication satellites, as well as ground and airborne terminals. Located in Israel, the UK, Bulgaria, and the US, we are a techno logy leader in satellite communication.
System Validation Engineer - Satellite Ground Station
This is an opportunity to embark on an interesting and challenging adventure into the world of satellite communication which is undergoing a major disruptive revolution.
The LS includes Control and data processing HW, SW as well as Phy and Radio HW and FW, to construct a full communication system supporting DVB-S2X as well as other Radio and IP communication protocols.
Responsibilities
Landing station system validation activity including Phy, HW and SW validation
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams
Define and write automatic test plans and test procedures for new systems and features
Build test setups for fully automated regression as well as for manual tests
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems
Record, investigate and analyze defects
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams
Support Test Management tools and continuous integration methodologies
Data analysis and post processing of data collected
Compilation of regular Test execution summary report with metrics.

Our Sat Connect IC business unit, a division of our Satellite Systems business is a leading provider of ASICs, software, multibeam electronically steered antennas, and complete systems for communication satellites, as well as ground and airborne terminals. Located in Israel, the UK, Bulgaria, and the US, we are a techno logy leader in satellite communication.
Responsibilities
System validation activity includes Phy, HW and SW validation
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams
Define and write automatic test plans and test procedures for new systems and features
Build test setups for fully automated regression as well as for manual tests
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems
Record, investigate and analyze defects
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams
Support Test Management tools and continuous integration methodologies
Data analysis and post processing of data collected
Compilation of regular Test execution summary report with metrics.

We are looking for a Verification & Validation Engineer to join our V&V and QA team. The position reports to the Group Manager, V&V, QA and is responsible for HW and FW testing of new products, maintaining high product quality, supporting the production floor, and contributing to the ongoing development of test automation.

The role includes:
Testing new products (HW, FW) and ECOs.
Performing functional testing and verifying compliance with MRD requirements.
Testing and evaluating video and audio quality.
Creating test scenarios that address customer use cases.
Preparing test instructions for the production floor, including scripts for automated testing.
Creating test plans and reporting bugs using Jira.
Supporting the production floor and OEM companies.
Contributing to the ongoing development of test automation.

Outstanding opportunity to be part of a super-cutting-edge team working on systems above and beyond the globe.



What you will be doing​



Writing system validation Test plans , Design and develop Test programs to validated embedded system features and performance.

Conducting System Validation Test cycles to verify systems based on HW (analog and Digital), RF, SW, FW

Experience with Python or C programing, Git or other programming languages & source control.

Strong technical troubleshooting.

Develop tools and utilities for Lab & field testing, feature analysis

High debug capabilities when work with the Software, systems, HW teams on complex issues.

Ability to move fast and decisiveness.

Building development environment.

Designing automate tests.

E2E ownership product from kickoff to production.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.

Required Senior DDR Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.
This role allows for independent work, impactful input, and substantial contributions to the VLSI departments verification tasks
Responsibilities:
Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.
Collaborating with Design and Verification Teams.
Contribute to Verification Planning and Coverage.
Define formal verification plans, track progress, and contribute to achieving verification completeness.

Required Emulation Verification Tech Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead, plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Required Junior AI SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will join a high-performing Research and Development team dedicated to delivering high-quality silicon. You will partner with cross-functional technical teams throughout the full development lifecycle, taking ownership of quality assurance strategies from the initial concept through final tape-out.
Responsibilities
Plan digital design block verification by analyzing specifications and identifying critical scenarios with design engineers.
Create and enhance constrained-random environments using SystemVerilog and Universal Verification Methodology (UVM), or execute formal verification using SystemVerilog Assertions (SVA) and industry-leading tools.
Identify and write all types of coverage measures for corner-cases.
Debug test failures alongside design teams to ensure block correctness.
Analyze metrics to resolve coverage gaps and drive progress toward tape-out.

Required Senior Verification Engineer, Digital Signal Processing, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you own the verification strategy for high-speed Physical Layer (PHY). You aren't just looking for RTL bugs, you are looking for system-level failures. You will lead the effort to verify how the digital DSP interacts with the analog front-end.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the verification strategy for high-speed PHYs (112G/224G), defining the test plan for top-level integration and mixed-signal boundaries.
Architect and implement mixed-signal verification flows using Real Number Modeling (RNM) or SystemVerilog-AMS to verify the interaction between Analog Front Ends (AFE) and digital DSP.
Design specialized testbenches to verify the stability, convergence time, and tracking capabilities of adaptive algorithms (e.g., LMS, Zero-Forcing) across Process, Voltage, Temperature (PVT) corners.
Develop tests that simulate real-world data center conditions, including link bring-up, auto-negotiation, and error-recovery protocols.
Act as the primary verification interface for the Signal integrity and Power Integrity (SI/PI) and Analog teams, ensuring that physical channel impairments (loss, crosstalk, reflections) are accurately reflected in the Design Verification (DV) environment.

Required ASIC Design Verification Engineer, Digital Signal Processing
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
Responsibilities
Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.