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We are looking for a Backend Engineer, Payments.
As part of your role, you will be developing new features for the Payments engine, working closely with our Product and Design teams.
You will work with a variety of web development technologies while utilizing continuous development and fully automated testing coverage.
As a senior developer youll be responsible for creating technical designs, mentoring and setting development standards for your team members.

we are hiring a Senior Backend Engineer to join the Platform Team in Tel Aviv-Yafo, Israel.
The Platform Team is dedicated to developing mobile platform, delivering a reliable, fast, and secure experience for mobile users.
What You'll Do:
Lead the backend development of the new mobile application.
Design, implement, and maintain high-performance microservices that support low-latency and high-throughput operations.
Develop and optimize ' mobile API to ensure a seamless and scalable experience for our mobile users.
Collaborate with cross-functional teams to design systems that meet operational and business goals.
Research and implement cloud-native architectures to support ongoing growth and scalability.

We are seeking a talented Backend Engineer to design and develop scalable, low-latency backend systems that power our cutting-edge applications.
The ideal candidate will have a strong foundation in modern programming languages and frameworks, with a focus on optimizing performance and handling large-scale data.

Required Senior Memory Subsystem Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Architect representative
Job Description
The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.

Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

Required Senior HW architect
About the group:
Highly experienced Group in switch processing including HW and SW architecture with deep background in the high-speed networking world. Our innovative packet processors are designed into the most advanced data centers by tier-1 vendors.
What will you be doing?
Definition of our next generation Packet Processor/Datapath/congestion management architecture for high-performance complex SoC Ethernet Switch.
Define the architecture from requirements to production.
Architecture & micro-architecture definition for the systems and its blocks.
Support the development group by delivering specs.

Required Senior Core Power Management Architect
Job Description
Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers.
The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invens corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

We are looking for a Principal Backend Engineer to join our Cortex backend engineering group.
The group develops and maintains the backend of Cortex products Cortex XSOAR, Cortex XDR, and Cortex XSIAM. The great majority of the Cortex engineering group is located in the TLV office which allows us to operate at a high pace with short loops of decisionmaking.
You will join a team focused on developing, innovating, and scaling the Cortex XSOAR product, along with contributing to shared Cortex infrastructures and components. We are looking for candidates with a cando attitude, who are passionate about complex problems and thrive on bringing value to thousands of customers.
More information about XSOAR, here.
Your Impact
Endtoend backend development of features and components across their entire life cycle (design, develop, test, deploy, maintain)
Work closely with peers across different teams and disciplines to shape solutions and integrate with other parts of the product
Contribute to teamwide efforts code reviews, design reviews, technical and architectural decisions
Production oriented approach with providing real time mitigation and solutions to production issues
Participate in a rotational on-call schedule to ensure the smooth operation of our production systems and provide real-time support for critical issues.