לוח משרות דרושים ASIC / VLSI

Join the Front-End Design team, at the core of our development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.

Your Impact:

Review micro-architecture specifications.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for an experienced STA Lead Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.
Responsibilities:
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO.
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success.
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition.
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

We are looking for Emulation & Prototyping Engineer
Roles and responsibilities:
Build and maintain FPGA/emulation platforms for large-scale SoC/ASIC designs.
Map RTL designs to FPGA/emulation platforms.
Develop test environments and infrastructure for HW/SW co-verification.
Support hardware bring-up and software validation on emulation platforms.
Collaborate with verification engineers to run regressions and accelerate debug cycles.
Optimize partitioning, synthesis, and runtime performance on emulation systems.
Work cross-functionally with RTL design, verification, and firmware/software teams.


We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities:
Join a team of VLSI frontend design engineers in Chain-Reactions projects.
Define, plan and implement our next chip in Chain-Reactions on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

We are in the early stages of a new project and looking for a talented Senior engineer to take on a key role, leading Verification efforts of major parts of our ASIC - from scratch
Roles and responsibilities:
Take ownership of Verification for large ASIC clusters.
Plan, build, and execute the Verification environment end-to-end.
Mentor and guide juniors/students.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

Be part of a team responsible for designing the next generation of mobile devices. The position includes responsibility for system analysis and SW/HW architecture design for high-speed and low-power interfaces, networking algorithms, or audio processing. This job requires a collaboration with multiple engineering teams in various geographical locations to define requirements, interfaces, interaction between SW and HW blocks, performance analysis, and more.

This role can be based in either Hod HaSharon or Haifa.
This position will be office 5 days per week based
As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.
An ideal candidate will have between 8 to 10 years of work experience in ASIC RTL design, CPU design, SoC integration, micro controller and interconnect IP design.
Responsibilities
Understanding the high-level specification and requirements of functional units of micro-controller and application processor products.
Define the Micro-architecture for an unit and developing its RTL, including all design stages.
Collaborate with verification team on the test plan development for the blocks and verification closure.
Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets.

We are looking for a Formal Verification expert specializing in RTL/ASIC verification to work on a new cutting-edge RISC‑V application processor. The role involves ownership of formal methodologies, verification strategy definition, and close collaboration with architecture and design teams to ensure full functional correctness of complex processor units.
An ideal candidate will have at least 8 years of work experience with various formal applications and tools.
This is a 5 days onsite position in Hod Hasharon
Responsibilities
Understand high-level specifications and detailed requirements for application processor design logical units.
Collaborate with cross functional teams such as architecture, design, and software teams on formal verification planning.
Formal Verification expert to lead all formal activities for a new RISC-V application processor.

As an RTL Verification Engineer, you will be responsible for complex logical units of a new, cutting-edge RISC‑V application processor, working closely with architecture, design, modeling, software, validation, and implementation teams to meet all functional requirements, including performance, power, and area (PPA) goals.
An ideal candidate will have at least 3 years of experience in one or more of the following: CPU, RISC‑V architecture, micro‑controllers, and memory or cache controller design verification.
This is a 5 days onsite position in Hod Hasharon
Responsibilities
Understand high-level specifications and detailed requirements for application processor design logical units.
Verification from plan to execution, build and own all functional verification stages of a unit within application processor.
Collaborate with cross functional teams such as architecture, design, and software teams on test plan development.
Deliver on time with tight schedule entire verification suite including full functional and code coverage closure before tape-out.

Are you ready to be part of a team that's pushing the boundaries of technology and innovation? At NVIDIA, we're leading the way in transforming computer graphics, PC gaming, and accelerated computing. We're now beginning the next era of modern AI computing. As a Backend Chip Integration Engineer, you will play a crucial role in building the future of our powerful technologies. This is an outstanding opportunity for those who are passionate about VLSI physical design and automation flows.

What you'll be doing:

Define chip interface and silicon interposer interface, focusing on their physical location and netlist.

Develop automation flows for chip integration and power grid implementation.

Perform power integrity analysis of the interposer power grid to ensure flawless performance.

Collaborate with cross-functional teams to successfully implement world-class solutions.

Contribute to the continuous improvement of our integration processes with your innovative ideas and expertise.

We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.

What you'll be doing:

Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.

Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.

Define the implementation of debug capabilities to support performance validation and improvements

Understand our system requirement and help define the POR of our switch product line.

Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.

Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.

Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.

we are a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? we are the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.
Here at our company, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.