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14/05/2025
Location: More than one
Job Type: Full Time
​​We are looking for highly motivated Engineers who love the challenge and the opportunity of a growing company. Join us and be a part of a small and dynamic team, which is revolutionizing the parallel processor architecture.
Requirements:
Qualifications:

BSc in Electronics Engineering or Computer Science.

10+ Years of industry experience in verification, full chip dev. cycle.

2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.).

Experience with System Verilog and UVM methodology - MUST.

Hands-on experience with two or more of the following :

PCIE (Gen5 and above).

DDR (v4 and above).

AMBA protocol family, (inc. AXI4+, ACE/CHI)

ARM core architecture.

Advantages:

M.Sc. in Electronics Engineering or Computer Science.

Working experience with Formal verification.

Scripting skills in Python/Perl/shell.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8176198
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14/05/2025
Job Type: Full Time
Design and develop TEST plans for VLSI circuits, including digital, analog, and mixed-signal circuits. Implement and execute TEST procedures to ensure the functionality and performance of VLSI circuits. Analyze TEST data and identify issues related to circuit design, manufacturing, and performance. Collaborate with design engineers to develop and optimize TEST methodologies. Develop automated TEST scripts and tools to improve TEST efficiency and coverage. Perform failure analysis and debug issues to identify root causes and implement corrective actions. Document TEST results, methodologies, and procedures for future reference. Stay updated with the latest advancements in VLSI testing technologies and methodologies.
Requirements:
Associate or bachelors degree in Electronics Engineering. Proven experience in VLSI circuit testing, including digital, analog, and mixed-signal circuits. Strong knowledge of VLSI design and testing methodologies. Proficiency in using TEST equipment such as oscilloscopes, logic analyzers, and automated TEST systems. Experience with scripting languages (e.g., Python, PERL) for TEST automation. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. Ability to work independently and manage multiple tasks effectively. Preferred Qualifications: Experience with industry-standard EDA tools (e.g., Cadence, Synopsys). Knowledge of semiconductor manufacturing processes and reliability testing. Familiarity with Imaging industry. Benefits: Professional development opportunities and continuous learning. Flexible work hours and remote work options. Collaborative and inclusive work environment. True contribution to future and safety of Israel. Location: SCD Bar-Lev site
Job Type: Full-Time.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8165773
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Ramat Gan
Job Type: Full Time
our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).
Requirements:
Proven Experience in either SCAN or MBIST tools and flows
At least 2 years of DFT experience in both SCAN/MBIST
At least 5 years of experience in the ASIC/SoC industry
Knowledge of Hierarchical SCAN methodology
Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows
Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG)
Knowledge in Automotive industry FuSa (Functional Safety)
Knowledge of Synthesis flows
Proven skills in Perl / Python / TCL
Excellent communication skills
BSEE/MSEE is required
If you are an experienced DFT engineer, seeking to learn, improve and to be challenged by new concepts and complexities in relation to DFT for Automotive - your place is with us!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170573
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Jerusalem
Job Type: Full Time
The company's EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.
Requirements:
BSc or MSc in Electrical and Electronics Engineering.
Proven Experience in either SCAN or MBIST tools and flows.
At least 2 years of DFT experience in both SCAN/MBIST.
At least 5 years of experience in the ASIC/SoC industry.
Excellent communication skills and team spirit.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170566
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דיווח על תוכן לא הולם או מפלה
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תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).
Requirements:
Proven Experience in either SCAN or MBIST tools and flows
At least 2 years of DFT experience in both SCAN/MBIST
At least 5 years of experience in the ASIC/SoC industry
Knowledge of Hierarchical SCAN methodology
Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows
Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG)
Knowledge in Automotive industry FuSa (Functional Safety)
Knowledge of Synthesis flows
Proven skills in Perl / Python / TCL
Excellent communication skills
BSEE/MSEE is required
If you are an experienced DFT engineer, seeking to learn, improve and to be challenged by new concepts and complexities in relation to DFT for Automotive - your place is with us!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170563
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The company's EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.
Requirements:
BSc or MSc in Electrical and Electronics Engineering.
Proven Experience in either SCAN or MBIST tools and flows.
At least 2 years of DFT experience in both SCAN/MBIST.
At least 5 years of experience in the ASIC/SoC industry.
Excellent communication skills and team spirit.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170558
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.
Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 5 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170521
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.
Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 5 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170505
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Jerusalem
Job Type: Full Time
our company EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
5+ years experience in the Physical Design field.
Experience with high speed interfaces (DDR/PCIE) - an advantage.
Experience with advanced nodes (5nm and below) - an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Building or maintaining implementation tools and flow - an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170480
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
our company's Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).
Requirements:
BSc/MSc in Electrical/Computer engineering
Proven Experience in either SCAN or MBIST tools and flows
At least 5 years of experience in the ASIC/SoC industry
Proven skills in Perl / Python / TCL
Knowledge of Hierarchical SCAN methodology
Knowledge of Logic BIST (LBIST) and Test Point Insertion (TPI) flows
Knowledge of TAP protocols IEEE 1149.1/1500/1687 (iJTAG)
Knowledge in Automotive industry FuSa (Functional Safety)
Knowledge of Synthesis flows
DFT experience in both SCAN/MBIST - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170447
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
our company EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.
Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
STA Expert (Prime-Time/Signoff).
8 years of experience in VLSI backend (RTL2GDS).
5 years of experience in full chip STA on complex SoCs.
Expert knowledge in timing closure & signoff methodologies.
Experience with DFT architecture, Async timing concepts & verification.
Experience in technically leading complex backend activities, preferably of complete SoC's.
Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8170317
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Petah Tikva
Job Type: Full Time
The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.
Requirements:
BSc in Electrical engineering/Computer Engineering.
Over 7 years of experience in Logic design.
Experienced in all ASIC flow from definition to implementation.
Experience in design for power- Advantage.
Experience in High-speed I/Fs or algorithm blocks - Advantage.
Knowledge in CDC and low power flow - Advantage.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8169100
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