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We are looking for an HPC and AI Data Center Engineer to join the networking cloud solutions HPC/AI Infrastructure team. We are focused on building supercomputers and HPC clusters based on groundbreaking technologies. We are looking for a lab manager, be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and GPU computing. Take part of building large-scale compute and Deep Learning software and hardware platforms, work together and support many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions.
What you will be doing:
Plan and build complex cluster and supercomputers in various of data center and labs
Rack stack and cable management to ensure efficient use of space and easy maintenance
Ensure data centers and labs power and cooling efficiency while optimizing rack space utilization
Data centers and labs daily operation and support
Installations for variety of infrastructure and solutions - Cloud, VMs, Storage, Network, HPC and AI
Perform troubleshooting - network, optic cabling, bare metal, operating system.
Support Research & Development activities.

Required Senior Manager, DPU Performance and System Validation
Join us as a DPU Performance and SV Manager and play a pivotal role in inventing the future of innovative computing technology! This is an outstanding opportunity to lead a dynamic team in Israel, boosting the performance of the entire DPU Chip Develop department to new heights.
What you'll be doing:
Lead and manage a group of 25+ engineers, coordinating two key teams: Performance in DV and Simulation Model, and System Validation.
Collaborate with the ARCH team to define and implement the Performance Verification (PV) Plan, ensuring comprehensive test coverage and platform integration.
Coordinate the performance emulation and functional validation processes, ensuring seamless readiness for TapeOut from a performance perspective.
Participate in post-silicon performance debugging, contributing to the flawless execution of performance improvements.
Develop and unify performance debug processes across all platforms, ensuring consistency and efficiency.

We are seeking experienced electrical engineers with a passion for system-level thinking and innovation in high-performance optical switch development. This role offers a unique opportunity to shape and deliver next-generation products that push the boundaries of high-speed optical communication.
What Youll Be Doing:
Lead and serve as the technical focal point for the integration of PHY system aspects and optical (CPO) electrical subsystems, ensuring their performance.
Hands on cross-disciplinary testing efforts and lab work, collaborating with system architecture, optics, silicon, thermal, mechanical, signal/power integrity, and software teams.
Characterization and testing of optical links using lab equipment (e.g., oscilloscopes, BER testers, optical spectrum analyzers and simulation tools).
Driving product scalability, working with internal partners-qualification teams to transition designs from prototype to high-volume production.
Documentation and reporting of design specifications, test results, and performance metrics.

We are seeking an QA engineer to join our SW/FW testing team. This position will be part of our growing team, which enables our products to meet the industry-leading benchmarks of efficiency and quality. We develop a collaborative and inclusive work environment, where ideas are shared and innovation is encouraged.
As a QA Engineer in this group, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards. We are looking for an ideal candidate with proven QA experience who will be actively involved in testing industry-leading features in the Networking sector, can acquire new feature knowledge, conduct both manual and automated tests, and contribute to the development of automation systems. The ideal candidate should bring a robust understanding for SW release cycle and the QA part in it.
What you'll be doing:
Review arch design and requirements documents for new features introduced in several domains like NVLINK Fusion, VR, GPUs and more.
Design and execute comprehensive test plans for both initial releases and ongoing firmware updates.
Develop and maintain automated frameworks expanding existing infrastructure with new capabilities to improve coverage, stability, and efficiency.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Conduct tests in various areas, including regression, performance, functional, and security. Keep track of testing progress and generate summary reports of testing activities.
Work multi-functionally with teams such as R&D, product marketing, and system verification to ensure high-quality, production-ready deliverables.
Define and build setups topologies for appropriate product coverage.

we are looking for a Compilation Technology Expert.

Job Description:
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.

we are looking for a AI architect/ microarchitecture.
Job Description:
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Lead next generation inference solution optimized for power, performance and area. Considering scalable solution for large scale systems with many resources. Covering efficient data delivery and workload map.

we are looking for a Computing Network & System Architecture Group Leader
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture.
As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

we are looking for a Senior Core Power Management Architect.
Job Description:
Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.

we are looking for a Senior CPU Core Architect.
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.