לוח משרות דרושים הייטק

our company is leading the way in groundbreaking developments in artificial intelligence, high performance computing and visualization. the gpu, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.
come work for the team that brought to you nccl, nvshmem & gpudirect. our gpu communication libraries are crucial for scaling deep learning and hpc applications! we are looking for a motivated partner enablement engineer to guide our key partners and customers with nccl. most DL /hpc applications run on large clusters with high-speed networking (infiniband, roce, ethernet). this is an outstanding opportunity to get an end to end understanding of the ai networking stack. are you ready for to contribute to the development of innovative technologies and help realize our vision?
what you will be doing:
engage with our partners and customers to root cause functional and performance issues reported with nccl
conduct performance characterization and analysis of nccl and DL applications on groundbreaking gpu clusters
develop tools and automation to isolate issues on new systems and platforms, including cloud platforms (azure, aws, gcp, etc.)
guide our customers and support teams on hpc knowledge and standard methodologies for running applications on multi-node clusters
document and conduct trainings/webinars for nccl
engage with internal teams in different time zones on networking, gpus, Storage, infrastructure and support.

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
at our networking, we are driven by innovation and excellence. our team in israel is looking for a dedicated chiplet layout owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing: be part of a cross-business-unit team and own the high-speed ip integration.
build a chiplet floorplan layout design from early assembly/planning through implementation and signoff.
work closely with partition owners and full chip sta engineers to assure high quality and timely convergence.
define and implement efficient, high-quality full chip/chiplet physical design tools, flows, and methodologies.
gain hands-on experience implementing the partition-level be design (rtl2gds).

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are now looking for a power optimization and analysis engineer! our company prides ourselves on having energy-efficient products. we believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. as part of the u/arch team in the switch group, you will be responsible for analyzing full chip and unit-level power data and driving the fe/be asic teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. key responsibilities include developing techniques to model, analyze, and reduce power consumption of our switches product line.
as a member of switch u/arch team, you will collaborate with architects, performance engineers, software engineers, asic design engineers, and physical design teams to study and implement power analysis and reduction techniques for our next generation switches. your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
what you'll be doing:
use internally developed tools and industry standard pre-silicon gate-level and rtl power analysis tools, to help improve product power efficiency.
develop and share best practices for performing pre-silicon power analysis.
perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
interact with architects and rtl designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
select and run a wide variety of workloads for power analysis.
prototype new architectural features in verilog and power analysis.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

lead a team of 5 engineers in the advanced technologies development
design and implement solutions throughout all layers from high level application, os and driver subsystem to firmware
work on impactful projects involving state-of-the-art high-performance computing hardware and software
provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology
collaborate with nvidia partners and customers

we are now looking for a best-in-class Verification engineer to join our outstanding gpu-networking silicon engineering team. as a dv engineer at gpu-networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - gpu super-chip. 
what youll be doing:
work in a dv (design verification) team that has a global responsibility over deliverable units and clusters to the silicon gpu
integrations and full-chip models
verification of chip blocks/entities according to specifications under challenging constraints
ramp-up and run dv tasks on emulation platform

we are seeking a highly motivated high-performance system architect to join our team of experts and help shape the future of high-performance and ml / ai computing. our next-generation nvl systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced ai models such as gpt and deepseek. as a high-performance system architect at nvidia, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.
what youll be doing:
define the nvl system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
research various of solutions to enable the next large-scale-high-performance computing clusters. the position spans over various layers from algorithms, software, firmware, and hw.
collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

our company networking is a leading supplier of end-to-end ethernet and nvlink intelligent interconnect solutions and services for servers, Storage, and hyper-converged infrastructure. the company hw microarchitecture group is looking for an extraordinary solution architect to participate in helping our customers to get the maximum performance from our network products. the successful candidate will show strong background in chip design (arch, microarch, design, dv), excellent system view, ability to work independently, good communication and motivation to solve sophisticated problems.
 
what youll be doing:
help customers get the best performance from our products.
debug sophisticated customers issues.
come up with solutions for current and future products.
work with teams and customers from around the world.
partner closely with our field engineers and architecture.

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our company is looking for an experienced dft design engineer to join the dft design team and develop the next generation dft technologies.
as a design engineer in the dft design team at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people.
today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an our employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team that is building ai platform for operating ai factories to make a lasting impact on resilient operations of ai clusters.
what will you be doing:
you will bring together and understand internal and external customer requirements to improve ai cluster resiliency and design aiops-based solutions that address these needs.
develop automated workflows for issue detection and root cause analysis and closely collaborate with operators to debug sophisticated, Full-Stack ai cluster problems. we will bring to bear the findings for product improvements!
deliver compelling technical presentations and lead hands-on demos or training. you'll also handle evaluation deployments (poc/pov) and ensure smooth, reliable installations by staying engaged and encouraging throughout the customer journey.