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We're seeking a BD Team Lead to own and grow our outbound business development function -

building pipeline across Balance's full product suite, including pay-by-invoice and order-to-cash

(O2C).

This role reports directly to the VP of Sales.

Benefits:

Mission-driven culture with a strong focus on personal growth.

Hybrid work model: 3 days per week in our Tel Aviv office.

Stock options.





Responsibilities
Lead and coach a team of BDRs, setting quota, pipeline targets, and day-to-day priorities.

Own outbound strategy and execution across Balance's full product suite.

Partner with Sales and Marketing to keep BDR-sourced pipeline aligned with target segments and ICP.

Report on team pipeline metrics and surface insights that inform BD strategy.

Recruit, ramp, and develop BDRs as the team scales.

We seek an experienced Senior Staff Data Engineer to join our AI and Data Solutions unit and champion an AI-first strategy. You will spearhead the development of Data Lakehouse processes, model core product domains, and define data engineering best practices across the organization. Serving as a technical project lead, you will provide strong direction and collaborate with Data Science, Analytics, R&D, and IT teams to elevate onboarding workflows. This role demands a proactive approach to optimizing system capabilities and driving cross-functional data initiatives.
Key Responsibilities:
Own the design, implementation, and optimization of scalable Data Lakehouse and Data Warehouse architectures across diverse cloud ecosystems.
Spearhead the development of robust ETL/ELT pipelines and data ingestion processes utilizing SQL, Python, PySpark, and DBT.
Apply advanced data modelling techniques to structure complex data assets into optimized facts, dimensions, and partitions.
Partner with cross-functional leadership across data science, analytics, R&D, and IT to identify requirements and improve workflows.
Orchestrate complex data workflows combining tools like Airflow and DBT with advanced Gen-AI development workflows using CloudCode.
Define, document, and popularize data engineering best practices, design patterns, and data quality standards across the unit.
Evaluate and implement modern data technologies spanning vendor-specific and open-source landscapes including GCP, AWS, and Apache Iceberg.
Provide technical direction and hands-on guidance to ensure high-performance execution, reliable pipeline delivery, and proactive problem-solving.

As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.


Job Description
The mission of this role is to perform system validation for our highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey in our company.

We are looking for an exceptional Senior / Principal Backend Engineer to join our AppSec Platform group, reporting directly to the Group Leader.
This is a highly autonomous, hands-on role for an engineer who wants broad technical ownership rather than a narrowly defined domain. You will work on some of AppSec's most important and challenging engineering problems - spanning high-scale distributed systems, data infrastructure, onboarding and integrations, developer experience, reliability, performance, and AI-driven engineering.
You will frequently operate across team boundaries, take ambiguous problems from idea to production, and lead technical initiatives that have an impact well beyond a single service or team.
We are looking for someone who combines deep backend expertise with strong execution: an engineer who can design the architecture, dive into the code, debug production systems, challenge existing assumptions, rapidly prototype new approaches, and bring others along with them.
Key Responsibilities:
Lead Critical Initiatives End-to-End - Own complex, business-critical engineering efforts from problem definition and architecture through implementation and production, often spanning multiple teams and domains.
Build and Scale the Backbone of AppSec - Design and evolve distributed systems and data infrastructure supporting large enterprise environments and hundreds of millions of entities, while balancing scalability, reliability, performance, and cost.
Stay Hands-On and Raise the Engineering Bar - Write and review production code, solve complex technical problems, and champion excellent architecture, maintainable code, testing, observability, and production ownership.
Drive Performance & Reliability - Identify architectural and operational bottlenecks and lead meaningful improvements in scalability, resiliency, efficiency, observability, and production readiness.
Shape DevEx and AI-Driven Engineering - Improve how engineers build, test, debug, and operate software while leveraging AI, automation, and agentic approaches to accelerate development and unlock new capabilities.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.

Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

PassportCard Labs is where innovation meets impact. As the technological powerhouse behind PassportCard, we design and build cutting-edge solutions that revolutionize the insurance industry. Whether it's real-time claims payments or predictive analytics, our Labs team is at the forefront of driving change and shaping the future of insurance. Ready to innovate with us? We are looking for an experienced Enterprise Architect to join us at a pivotal time . Our technology organization is in the midst of a significant transformation journey, including large-scale modernization of core insurance platforms, migration toward cloud-native and event-driven architectures, expansion of AI-powered business and engineering capabilities, adoption of agentic software development practices (AI-DLC), and the creation of a next-generation digital platform for insurance, payments and customer services. What you'll do: Define and evolve our enterprise architecture and technology strategy. Lead modernization of core platforms — policy administration, claims, underwriting, pricing, and customer/CRM systems. Drive cloud-native, event-driven, and microservices architecture at scale. Lead real, hands-on adoption of AI-DLC and agentic software delivery. Design RAG architectures, knowledge graphs, MCP-based systems, and multi-agent architectures. Establish AI governance, security, and evaluation frameworks for AI-generated code and analysis Own vendor/platform selection, build-vs-buy decisions, and technical debt strategy Partner with executives, product, and engineering leaders to turn strategy into architecture



Business Unit:
PassportCard Labs

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging.
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies.
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market.

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs.
Ensure rapid cycles from RTL to functional stability through systematic debug approaches.
Own technical blocks and drive them to completion independently.

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios.
Ensure seamless hardware-software integration for AI infrastructure connectivity.
Collaborate with Design and Verification teams to optimize emulation strategies.

As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.

This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.

Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products.
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems.
Analyze system requirements and translate them into scalable and efficient hardware architectures.
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering.
Define and review micro-architecture specifications and ensure alignment across teams.
Contribute to standard-based and custom protocols for next-generation AI infrastructure.
Support performance modeling, simulation, and architectural validation.
Work closely with customers and partners to understand emerging use cases and requirements.
Mentor engineers and help build strong technical leadership within the Israel R&D center.