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מיקום המשרה: רמת גן וחיפה
דרושים בוגרי תואר ראשון מדעים מדויקים, בעלי מיומנויות אוטודידקטיות ואוריינטציה טכנולוגית, להשתתפות במסלול קריירה בפיתוח תוכנה ללא עלות והשתלבות במגוון משרות פיתוח בחזית ההייטק הישראלי.
אינפיניטי לאבס הינה חברת מחקר ופיתוח המפעילה משנת 2014 מסלולי קריירה בתחומי ההייטק השונים.
החברה מחזיקה במתדולוגיה ייחודית במסגרת של צוותים אורגניים בהובלת מנטור מנוסה. הסטודנטים שלנו נבחרים בקפידה לתהליך, הן בשל הרקע האקדמי/התעסוקתי איתו הם מגיעים והן בשל מאפיינים של מצויינות.
בהכשרה תתרגלו פרקטיקות עבודה מובילות בתעשייה, תעבדו על פרויקטים מורכבים ותלמדו איך ללמוד בעצמם כל טכנולוגיה ברמה תעשייתית גבוהה.
כ-2,500 מבוגרי התוכנית השתלבו במשרות הדורשות 2-3 שנות ניסיון, ב-300+ חברות הייטק, חברות ביטחוניות, סטארט-אפים ומרכזי פיתוח, מהמתקדמים והבולטים ביותר בתעשייה.
ההכשרה על חשבוננו במהלך ההכשרה המטרה היחידה שלנו היא למצוא לכם את המשרה הראשונה בפיתוח תוכנה, מכיוון שההצלחה שלנו נובעת בהכרח מתוך ההצלחה שלכם
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לפני 10 שעות
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time
Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university

5+ years of experience in the filed

knowledge with UVM and functional verification methodologies
This position is open to all candidates.
 
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לפני 11 שעות
Location: Caesarea
Job Type: Full Time
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Requirements:
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 11 שעות
Location: Caesarea
Job Type: Full Time
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure
Requirements:
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 11 שעות
Location: Caesarea
Job Type: Full Time
In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.
Requirements:
* Bachelors degree in Electrical Engineering or Computer Science.
* At least 6 years of experience in software development/validation.
* Developing complex software in Python/C++.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Haifa
Job Type: Full Time
our eyeq platform group (epg) is seeking a motivated formal Verification engineer to join our team and contribute to development of hardware verification environments.
this position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
this is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle. what will your job look like:
be the owner of formal verification environment from first draft to sign-off stage
apply formal methods to verify the correctness of various complex digital systems
work with hw architects/designers to define assumptions, rules and cover properties
help define the formal verification methodology and environment to be applied by the team
explore new formal methods and tools
work with tools like cadence jaspergold, verisium manager, xcelium, indago
analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
develop generic formal blocks/functions of commonly used logic, to be later used off the shelf
Requirements:
all you need is:
bsc in electrical engineering, computer engineering, or Computer Science
passion for the field of formal verification
5+ years of experience in formal verification
experience coding system -verilog hardware description language
experience with scripting languages (e.g. Python, tcl)
strong analytical and problem solving skills
ability to work independently and in a team-oriented environment we change the way we drive, from preventing accidents to semi and fully autonomous vehicles. if you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Haifa
Job Type: Full Time
Our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.
Requirements:
all you need is:
bsc in electrical engineering, computer engineering or Computer Science
7+ years of experience working in verification environment, tests, and TEST bench development ( C / C ++/sv)
testplan defining and coverage-driven verification experience
fullchip/ SOC verification experience, strong system understanding
good debug capabilities using the latest eda tools
knowledge in industry standard protocols such as axi/acel/ocp/chi
sw Embedded experience, C / C ++ skills - advantage
strong skills in scripting PERL / Python - advantage
system verilog writing skills, preferably in ovm/uvm - advantage
3rd-party ips integration testing experience - advantage mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. if you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, and system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning and TEST execution to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with systemverilog assertions (sva) and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
experience verifying digital logic at rtl level using systemverilog or Specman /e for fpgas or asics.
preferred qualifications:
master's degree or phd in electrical engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
experience with verification techniques, and the full verification life cycle.
experience with performance verification of asics and asic components.
experience with application-specific integrated circuit (asic) standard interfaces and memory system architecture.
knowledge of cpu/processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like arm, x86 or risc-v, is highly beneficial for verifying processor cores or ip blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
google system infrastructure builds the cloud for google services and for google cloud customers, by solving business TEST of performance and cost, utilizing hardware, software, and system solutions.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving team behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification strategy, identify the platform to validate reasoning components.
define the TEST plan and strategy with stakeholders, including sign-off and exit criteria.
plan and execute the verification of internet protocols (ips) using dynamic verification and formal verification.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, Computer Science, or equivalent practical experience.
10 years of experience in managing design verification (dv) team.
experience with verifying units using formal and design verification methodologies.
experience in verification methodologies, tools, and techniques.
experience in leading technical teams and building cross-functional relationships.
preferred qualifications:
master's degree or phd in electrical engineering or Computer Science.
4 years of experience in managing design verification (dv) team.
experience in working with one or more formal verification tools (e.g., jaspergold, vc formal, questa formal, 360-dv).
experience with verification techniques, and full verification life-cycle.
experience in leading teams and delivering projects.
excellent communication skills, with the ability to present technical concepts to audiences.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering or equivalent practical experience.
4 years of experience working with design networking like remote direct memory access (rdma) or packet processing and system design principles for low latency, throughput, security, and reliability.
experience creating and using verification components and environments in standard verification methodology.
preferred qualifications:
2 years of experience working with design networking.
experience in verifying digital systems using standard internet protocol (ip) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
experience in transmission control protocol (tcp), ip, ethernet, pcie, and dynamic random-access memory (dram), network on chip ( NOC ) principles and protocols.
experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance TEST plans.
experience with verification techniques and the full verification lifecycle.
experience with performance verification of asics and asic components.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Haifa
Job Type: Full Time
We are looking for a Verification Team Leader for our team in Haifa to drive verification for next-generation PHY IPs . The PHY DV team operates at the intersection of verification, research, and innovation, continuously improving techniques, models, and flows to increase the efficiency and quality of PHY verification. This is a hands-on technical leadership role, combining deep verification expertise with team leadership and close collaboration with design, architecture, firmware, and system teams.
Description
Lead the verification team, including hiring, planning, and communication with management.
Strong teamwork and communication skills.
Responsibilities
Lead the verification team, including hiring, planning, and communication with management.
Define verification architecture and lead for execution
Own verification methodologies, standards, and best practices across the team
Requirements:
BSc in Electrical Engineering
8+ years of industry experience, verification team leadership
Strong DV background, proficiency in SystemVerilog and UVM
Experience with low-power verification, formal, FW verification, or Emulation is a plus
Define verification architecture and lead for execution
Ability to lead teams to high-quality outcomes
Own verification methodologies, standards, and best practices across the team
Drive improvements in verification flows and methodologies
Collaborate closely with design teams on specifications, architecture, test plans, and testbench development
Strong teamwork and collaboration skills
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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26/02/2026
Location: Caesarea
Job Type: Full Time
We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of System Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SoC architecture, CPU subsystems, and multi-core designs.
This position is open to all candidates.
 
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25/02/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.
Requirements:
Basic Qualifications:
- Electrical/Computer Science engineer. Please include a grade sheet/academic transcript along with your CV in a single PDF when submitting your application.
- knowledge of object-oriented programming concepts.
- knowledge of Verilog/SystemVerilog/Specman.

Preferred Qualifications:
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification).
- Knowledge of the following programming languages: Perl/Bash/TCl/Python.
- Knowledge of PCIe, Processors, Ethernet, DDR.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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24/02/2026
Location: Haifa
Job Type: Full Time
we are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.
Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Haifa
Job Type: Full Time
The Design V&V Lead is responsible for managing Haifa-based V&V team members and for planning and coordinating V&V project activities.
The Haifa-based team members are part of an integrated V&V team located in Israel, the United
States, and Poland.



The V&V Lead will also support product development activities as a Test Engineer by designing and implementing detailed, comprehensive, well-structured test plans and test procedures.
The V&V Lead will need to have people management experience, as well as technical experience, including instrumentation, medical device V&V, and test method validation.
The V&V Lead should be creative and proactive to work successfully in a fast-paced environment, contributing to early prototype evaluations, test method development, design feedback to engineering teams, defect identification, and troubleshooting.



This is a full-time, exempt position located in our Haifa, Israel office and reports to the Verification and Validation Manager.









ESSENTIAL DUTIES AND RESPONSIBILITIES:

Line manager to Israel-based V&V Test Engineers and V&V Test Technicians for design verification activities.
Contribute to continuous improvements of the quality system and V&V process as part of the integrated V&V team across multiple locations.
Lead a team of different role types and varying levels of experience to perform the design V&V activities in support of product development activities.
Engage with leadership and cross-functional peers to ensure the design V&V team is integrated into the product development process, meeting both product quality and milestones on time.
Coordinate V&V activities of product development and sustaining projects.
Serve as signature alternate for V&V Manager on project-level documents, when appointed.
Execute V&V engineering work as an individual contributor when needed:
Plan test strategy and establish clear traceability between requirements and test procedures.
Analyze requirements and write test procedures with robust coverage of requirements using different test scenarios.
Write instruction-based test procedures and design test fixtures and/or SW tools as needed.
Guide and participate in the review of team members work output (above bullets) as needed to ensure a consistent quality level.
Train V&V team members on the quality system and V&V process.
Requirements:
B.S. Degree in Engineering or other technical discipline; OR Secondary school diploma, plus relevant work experience




Knowledge:

At least 5 years of medical or related industry experience in product development and/or testing.
V&V for medical device experience is preferred, or V&V in a related field with similar controls.
At least 2 years of management or leadership experience / Proven ability to manage a V&V team.
Strong verbal and written communication skills in English, including ability to give clear direction to team members.
Experience in designing, writing, reviewing, and performing design verification tests .
Experience organizing and planning test efforts.
Experience designing and creating test fixtures.
Experience in medical device product development preferred.
Familiarity with measurement uncertainty analysis and test method validation.
Demonstrated technical writing skills.
Strong grasp of fundamental engineering concepts, basic principles.
Critical thinking and decision making, including the ability to recognize when to ask questions.
Highly organized and strong attention to detail.
Capable working in a multi-disciplinary environment involving software, hardware, and mechanical engineers.
Able to work in a team environment and execute responsibilities with minimal direct supervision.
This position is open to all candidates.
 
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