לוח משרות דרושים חשמל ואלקטרוניקה

Requirements:
PhD or MSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 15 years of relevant research and development experience in industry and academia in the following areas:
- Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
- Workload characterization and analytical model generation
- System Modelling and emulation of HW
- Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and an international vision
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners
Excellent oral ability to provide innovation and an international vision
Excellent communication, presentation and reporting skills
Excellent oral and written English. written English.

Requirements:
REQUIREMENTS:
Bachelors degree in computer science, Electrical/Computer engineering Must.
At least 5 years of experience in microprocessors coding such ARM Cortex-M series Must.
Familiarity with real-time embedded systems design and low-level hardware interactions such SPI, I2C, UART, CAN, etc.
Familiarity with MCU architecture and system peripherals such ADC, DMA, PWM, TIMERS, GPIOs, SYS CLOCKS, etc.
Deep understanding of the C language, basic understating in C object-oriented or C++ Must.
Software Development skills proficient understanding SW development cycle, coding standard, debugging, source control, writing design documentations.
Proficient with lab equipment with emphasis on Oscilloscope, logic analyzer and power supply Must.
Interpersonal abilities: Team player, Independent, Fast learner, hardworking, reliable Must.
Excellent communication skills in Hebrew and English both written and verbal.

ADVANTAGE:
Experience in Hardware and Power electronics.
Proficient understanding of C object-oriented or C++ Big advantage.
The automotive industry comply coding such as MISRA-C:2004.
Experience in working with IAR/ Keil embedded workbench.

Requirements:
BSc. in Electrical Engineering (from known university)
Minimum 8 years of experience Must!
Logic design project leader or chip architect
Hands on RTL design with Verilog or System Verilog
Micro architecture definition in CPU/DSP environment
Knowledge in verification (System Verilog, System-C etc.)
Knowledge and experience in the following is advantage:
RTL for FPGA and emulation
AC spec definition
SDC timing constraints write from spec
RT C, C++ ,assembly
Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC
Hands on spyglass, synthesis, STA, DFT
Experience with technical customers support or interface

Requirements:
5 years hands-on System Verilog RTL coding.
Experience with tools such as VCS, Verdi, and Spyglass.
Experience debugging and working with validation using UVM.
Experience with Multiple Clock Domains, multiple power domains, low power design.
Knowledge and experience in the following is advantage:
Experience with SoC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
Experience with clock crossing interface like Gray FIFO, CDC.
Experience with Pre silicon Validation, UVM codding, Validation tools and methodology.
Experience in Full design cycle including BE design, Synthesis, Static Timing, floor planning, DFT integration.
RTL for FPGA and emulation
Experience with software and with C/C++ for reference model development. Developed drivers for ARM SoC IPs .

Requirements:
5 years of SoC System Verilog validation experience.
Hands on experience using UVM to verify ASICs.
Advanced knowledge of System Verilog test-bench language.
Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations, formal validation.
Knowledge and experience in the following is advantage:
Experience with the full digital design verification cycle -- from spec through bring-up and prototyping and debug systems.
Experience with performance, power validation, digital design (RTL), and formal verification.
Experience with SOC design in DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, and ARC CPU
Experience with mixed signal verification methodology for IPs such as PHYs, A2D, PLLs etc.
Experience with software and C/C++ for reference model development. Developed drivers for ARM SoC IPs.

Requirements:
BSc. in Electrical Engineering (from known university)
Minimum 5 years of experience Must!
Technical management experience Advantage
Knowledge and experience in the following is advantage:
Floor plan and Place & Route, Block & Top level
Timing Closure & debug, STA, SDC insertion and analysis.
Clock Tree Synthesis
Power Grid Analysis
LVS/DRC Debug
DFT & ATPG methodologies (BIST, Scan, JTAG)
CAD Experience: Synopsys preferred , Cadence acceptable

Requirements:
BSc. in Electrical Engineering (from known university)
Minimum 2 years of experience Must!
Knowledge and experience in the following is advantage:
Floor plan and Place & Route
Timing Closure & debug, STA
Clock Tree Synthesis
Power Grid Analysis
LVS/DRC debug
Experience with DFT - Advantage
Experience with ICC Advantage

Requirements:
BSc. in Electrical Engineering (from known university)
Minimum 3 years of experience on DFT Must!
Knowledge and experience in the following is advantage:
Knowledge and experience with DFT methodologies (Scan, ATPG, @speed, memory BIST, I/O DFT)
Scan insertion and ATPG experience for stuck-at, transition delay, bridging and IDDQ
Coverage improvement and DFT DRC analysis using FTMAX / DFTCompiler / TetraMAX / SpyglassDFT - Memory BIST using Tessent MBIST (MentorGraphics)
Strong knowledge of JTAG 1149.1, 1149.6 and P1500 standards
Hands on design and implementation experience in DFT features
In depth understanding of DFT tool flows and methodologies (Synopsys or mentor or any other equivalent tools).Mentor Tessent MBIST experience is an added advantage
Hands on experience in end to end design flow (conception to TO to production) in DFT
Experience using Perl or other UNIX scripting languages for flow automation
Experience with Formal equivalence checking
Experience with setting up and running gate level simulations