לוח משרות דרושים &nbsp;מהנדס חשמל במרכז, לחיפוש זה נמצאו 416 משרות

06/08/2026

Emulation Engineer

Location: Giv'atayim

Job Type: Full Time

we are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.

Responsibilities
Develop and build complex emulation models for coming generations of accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system

Requirements:
Requirements
B.Sc. or higher degree in Electrical Engineering from a leading institution
3+ years experience in building emulation models, running tests on emulation machines, and debugging issues within the time constrictions of silicon design projects while handling multiple priorities
Experience with emulation platforms such as Palladium, Veloce, or Zebu, including compilation, debug, power, performance, and throughput tuning.
Familiarity with Linux environments
Experience with languages such as : C, C++, Perl, Ruby, System Verilog, Verilog, Make
Familiarity with interfaces such as PCIe, SPI, UART, ETH: advantage
Familiarity with embedded systems: advantage
Knowledge of FPGA: advantage

This position is open to all candidates.

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06/08/2026

Hardware Technical Program Manager

Location: Giv'atayim

Job Type: Full Time

We are seeking a talented Program Manager to join our team. In this high-visibility, hands-on role, you will drive forward the development of our chip by managing the complete program lifecycle, from architecture to successful tapeout, ensuring deliverables meet scope, schedule, and quality requirements.

Responsibilities
Lead the planning, development and implementation process of cross-functional teams focused on product delivery.
Drive the execution of the hardware roadmap by managing the complete lifecycle from architecture definition to tapeout.
Partnering tightly with Architecture, RTL Design, and Design Verification (DV) leads to identify bottlenecks, track coverage metrics, and mitigate risks before they impact the tapeout schedule.
Define the core operational processes and modes of work for the entire HW group, building and refining the stage-gate reviews required to transition smoothly from architecture into implementation and verification.
Oversee project monitoring, reporting, and risk management, from initiation to delivery, addressing intergroup dependencies to ensure timely and successful completion.
Lead process and methodology improvements, proactively addressing issues to achieve business goals.

Requirements:
Requirements
BS in Computer Science, Computer Engineering, or another relevant technical field, or equivalent practical experience.
6+ years of experience in technical program or project management of software engineering projects supporting large scale software and hardware groups.
Experience leading the full silicon development lifecycle, managing cross-functional hardware programs from architecture and Design Verification (DV) through tapeout.
Hands-on experience with project management methodologies, preferably Agile, and tools-ideally Jira.
Excellent problem solving, organizational and analytical skills, with a proven ability to take initiative and build strong and productive working relationships.
Excellent communication and management skills.
Familiarity with.
Hardware background: an advantage.
Customers facing experience : an advantage

This position is open to all candidates.

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06/08/2026

Logic Design Team Lead

Location: Giv'atayim

Job Type: Full Time

we are looking for a talented and experienced design manager to drive and help our group to get to the next era of computer architecture. In this position, you will design the critical parts of future chips. You will be involved in the full design cycle from architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Be accountable for your team's milestones & timelines
Leading your team members and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum

Requirements:
Requirements
B.Sc. in Electrical Engineering or Computer Science
8+ years of digital design experience with complex blocks
5+ years as a design team leader
Ability to transform requirements into specification documents
Proven record in high-speed and low-power design
Experience in front-end tools and analysis: CDC, LINT, power, simulation
Experience in network design (ETH) is an advantage

This position is open to all candidates.

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06/08/2026

Physical Design Manager

Location: Giv'atayim

Job Type: Full Time

we are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product

Responsibilities

Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip

Requirements:
Requirements
7+ years of physical design experience, working on complex subsystems
Experience in leading BE projects, subsystems and or complex high speed blocks
Experience in leading people (technical and or managerial )
Experience working in advanced node implementation flows
Good Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route.
Good understanding and experience in physical design verification methodology for debugging LVS and DRC issues at chip and block level
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
Working knowledge of extraction and STA methodologies and tools
Good capabilities of scripting languages, such as Perl, Python and Tcl

This position is open to all candidates.

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06/08/2026

Physical Design Team Leader

Location: Giv'atayim

Job Type: Full Time

Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!

Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

Requirements:
Requirements

7+ years of physical design experience
At least 2 years in technical leadership and/or people management roles.
Proficient in EDA tools such as Synopsys, Cadence, and Mentor for physical design tasks such as floor planning, placement, clock tree synthesis (CTS), routing, and timing analysis.
Expertise in timing closure, power analysis, and optimization methodologies.
Strong understanding of physical verification concepts, including DRC (design rule checking), LVS (layout versus schematic), and sign-off procedures.
Excellent team player with strong mentorship and management skills.
Demonstrated problem-solving capabilities and ability to thrive in a fast-paced, collaborative environment.
Effective verbal and written communication skills to interface with cross-functional teams and provide technical guidance.

This position is open to all candidates.

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06/08/2026

Senior Design Engineer-CPU

Location: Giv'atayim

Job Type: Full Time

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up .

Responsibilities
Learn high performance RISC-V Arch and algorithms
Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

Requirements:
Requirements
6+ years of experience in complex ASIC designs
VLSI expert with a deep understanding of chip architecture and design flows
Excellent interpersonal skills, able to drive colleagues to achieve the project goals
Experience in design for timing and power
Experience working with various front-end tools and flows (CDC, LINT, Synthesis, etc)
Experience in high frequency or CPU design - an advantage

This position is open to all candidates.

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06/08/2026

Senior Logic Design Engineer

Location: Giv'atayim

Job Type: Full Time

we are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

Requirements:
B.Sc. in Electrical Engineering or Computer Science
6+ years of digital design experience with complex blocks
Ability to transform requirements into specification documents
Proven record in complex design
Experience in front-end tools and analysis: CDC, LINT, power, simulation
Team player, versatile and results-oriented
Experience in Floating-Point Unit is an advantage

This position is open to all candidates.

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06/08/2026

Senior Physical Design Engineer

Location: Giv'atayim

Job Type: Full Time

we are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration

Requirements:
Requirements
7+ years of physical design experience, leading complex process designs
In-depth knowledge of process and circuit design
Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route
Experience developing and implementing power-grid and clock specifications
Good command of industry-standard physical design and synthesis tools
Understanding of scripting languages, such as Perl and Tcl
Working knowledge of extraction and STA methodologies and tools
Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power
Leading projects and managing small groups: advantage

This position is open to all candidates.

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06/08/2026

למרכז הרפואי דרוש /ה מנהל /ת תחום מחלקת חשמל

מיקום המשרה: רמת גן

סוג משרה: משרה מלאה

אחריות על אחזקת מערכות החשמל ברחבי בית החולים.
ניהול והנחיית טכנאים בתחום החשמל ומנהלי משנה לאחזקת שבר ואחזקה מונעת במערכות החשמל.
הפעלת קבלנים בתחום מערכות חשמל לאחזקת שבר ואחזקה מונעת.
מעקב אחר תקלות שבר ומענה לתקלות מורכבות בתחום החשמל בהתאמה לנורמות שירות שהוגדרו.
ניהול תכנית העבודה בתחום האחזקה המונעת במערכות החשמל.
תאום עבודות החשמל למול הגורמים הרלוונטיים ברחבי בית החולים.
ניהול תחום הבטיחות במסגרת עבודות האחזקה.

דרישות:
הנדסאי / מהנדס חשמל - חובה
רישיון חשמלאי ראשי מתח גבוה - חובה
ניסיון של 5 שנים לפחות בניהול והנחייה של צוות עובדים - חובה
ניסיון משמעותי בניהול אחזקה בתחום החשמל, וניסיון בתעשייה או במתקנים כמו בתי חולים ותחנות כוח - חובה
ניסיון בניהול פרויקטים, יכולות ניהול וארגון, ושליטה ביישומי מחשב (Office) - חובה
שליטה בקריאת שרטוטי חשמל - יתרון משמעותי
ידע וניסיון בתפעול ושימוש בתוכנות לניהול תחזוקה - יתרון משמעותי
יכולת עבודה בסביבת מרובת ממשקים והתמודדות עם מצבים מורכבים
יכולת התמודדות עם עומס משימות ועמידה בלוחות זמנים
יחסי אנוש טובים ותודעת שירות גבוהה ויכולת מתן מענה לצרכים של אוכלוסיות מגוונות המשרה מיועדת לנשים ולגברים כאחד.

עוד...

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06/08/2026

Chip Design Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

We are now looking for a Chip Design Engineer to join our Switch Silicon team for Verification / Design roles. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design, implement and verify the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a combined design and verification team which develops some of the switch silicon core units.

Micro-architecture for RTL and simulation environment planning for units and modules.

Design/Verify RTL units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

Build reference models, verify, and simulate chip blocks/entities according to specifications.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, Full chip Micro-Architecture, BE, and FW.

Requirements:
B.Sc. in Electrical Engineering or Computer Engineering with high scores or equivalent experience.

1+ years of experience in RTL design and/or dynamic verification.

Completion of programming and logic design courses.

A great teammate with good communication and interpersonal skills.

This position is open to all candidates.

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06/08/2026

Senior Full Chip Layout and Physical Verification CAD Engineer

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.

Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.

Proficiency using Python, Tcl, Shell, Make scripting.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Self-motivation, attention to detail, and good interpersonal skills.

Ways to stand out from the crowd:

Experience with data collection and analysis

Experience in methodology definition / flow owner of Full-chip / Place and Route

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

This position is open to all candidates.

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06/08/2026

Senior VLSI Integration Engineer

Location: More than one

Job Type: Full Time

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

7+ years of actual design experience in chip design.

Solid hands-on RTL design skills in System-Verilog.

Proficiency in at least one scripting languages like python, bash, tcl.

Great teammate.

Way to stand out from the crowd:

Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers

This position is open to all candidates.

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8771283

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06/08/2026

Senior Switch System Validation Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

Our Networking System Validation Group is growing, and we are hiring a Senior Switch System Validation Engineer. As a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. You'll gain networking and Switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like Quality-of-Service, performance, logic correctness, and AI features. You will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages.

You should have a good grasp of software development in different fields, such as Python Scripting, embedded software, and device firmware. It's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans.
 

What you will be doing:

Work in a combined design and verification team specializing in Switch Full Chip works.

Understand the Switch architecture and build on test plan accordingly.

Develop Full Chip test collaterals/suites, maintain regressions, debug failures and sign-off coverages.

Maintain test suites to facility Emulation and/or Silicon platforms checkout as well.

Requirements:
What we need to see:

B.Sc. in Electrical Engineering, Computer Engineering, or Computer Science.

4+ years of experience.

Knowledge in Python and experience with C and C++ in a Linux environment.

Understanding and familiarity of networking designs and micro-architecture.

Outstanding ability to communicate, clearly present one's ideas, and able to work as a team.

 
Ways to stand out from the crowd:

Prior knowledge/experience with network protocols.

Experience with Object Oriented Programming, Operating Systems and Multi-Threaded application development.

This position is open to all candidates.

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8771262

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06/08/2026

Senior FC Verification Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

We are looking for a Senior verification engineer to join our FullChip Switch Silicon team. As a FullChip verification engineer in our Networking business unit, you'll join a group of passionate and talented engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a Full Chip verification team that is responsible to integrate and verify our Switch products at system level.

Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the switch.

Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.

Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.

5+ years of experience in verification, advantage for FullChip/SoC.

Knowledge in network protocols - advantage.

Deep knowledge in Specman - advantage.

A team player with good communication and interpersonal skills.

This position is open to all candidates.

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06/08/2026

Senior Design Integration Engineer

Location: Tel Aviv-Yafo

Job Type: Full Time

We are seeking for an expert in SOC Design Integration Engineer with strong design fundamentals, to work in Switch Silicon group. You'll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a design integration team which responsible for all the switch design integration.

Work closely with multiple teams within organizations such as Architecture, u-arch, designers, BackEnd and FW.

Work on FullChip Assembly and drive cross-functional teams towards FullChip milestone execution.

Be responsible for all the switch chip design architecture focusing on timing, area and power.

Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.

5+ years of experience in RTL design integration.

Experience in synthesis, physical design and DFT is a plus.

Background in RTL Build and Design Automation is a plus.

A team player with good communication and interpersonal skills.

This position is open to all candidates.

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8771246

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