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our company, an AI-first company, is revolutionizing how visual content is created. With a mission to bridge the gap between imagination and creation, we are dedicated to bringing cutting-edge technology to the creative and business spaces.
Our advanced AI photo and video generation models, including our open-source LTXV model, power our apps and platforms, including Facetune, Photoleap, Videoleap, and LTX Studio, allowing creators and brands to leverage the latest research breakthroughs, offering endless control over their creative potential. Our influencer marketing platform, Popular Pays, provides creators the ability to monetize their work and offers brands opportunities to scale their content through tailored creator partnerships.
What you will be doing
As an ML Software Engineer with a focus on low-level and CUDA-based optimizations, you will play a key role in shaping the design, performance, and scalability of our companys machine learning inference systems. Youll work on deeply technical challenges at the intersection of GPU acceleration, systems architecture, and ML deployment.
Your expertise in CUDA, C/C++, and performance tuning will be crucial in enhancing runtime efficiency across heterogeneous computing environments. Youll collaborate with designers, researchers, and backend engineers to build production-grade ML pipelines that are optimized for latency, throughput, and memory use, contributing directly to the infrastructure powering our company's next-generation AI products.This role is ideal for an engineer with strong systems-level thinking, deep familiarity with GPU internals, and a passion for pushing the boundaries of performance and efficiency in machine learning infrastructure.
Responsibilities
Design and implement highly optimized GPU-accelerated ML inference systems using CUDA and low-level parallelism techniques
Optimize memory, compute, and data flow to meet real-time or high-throughput constraints
Improve the performance, reliability, and observability of our inference backend across diverse compute targets (CPU/GPU)
Collaborate with cross-functional teams (including researchers, developers, and designers) to deliver efficient and scalable inference solutions
Contribute to ComfyUI and internal infrastructure to improve usability and performance of model execution flows
Investigate performance bottlenecks at all levels of the stackfrom Python to kernel-level execution
Navigate and enhance a large, complex, production-grade codebase
Drive innovation in low-level system design to support future ML workloads.

As a Partner Success Manager, you will work closely with our Partners to enable them to build a successful customer success practice. You will be the CX point-of-contact with your aligned Partners, helping them drive software adoption and accelerate the customer lifecycle. Your responsibilities will include:
Enabling key Partners to own the adoption of our Software through available programs.
Supporting partners in delivering Success Programs and initiatives with their customers, and providing insights to optimize these programs.
Facilitating workshops and training sessions to educate partners on our products, using successful case studies to drive onboarding.
Acting as a liaison between Partners and our CX product teams, sharing feedback to advise on product development and improvements.
Supervising and reporting on the progress of adoption initiatives, assessing their impact, and iterating on strategies as needed.
Managing services and service creation.

Join the Silicon One PHY System Team, a key part of silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.

Your responsibilities will include:
Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY firmware and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.

As a Signal/Power Integrity Engineer, you will play a key role in ensuring the performance and reliability of our high-speed SerDes IP, covering silicon, package, and board-level analysis. You will collaborate across multiple fields, including analog design, silicon integration, PCB & package design, and mechanical engineering.

Provide implementation guidelines and feedback to silicon, package, board, and system design teams.
Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS.
Conduct feasibility studies, design verification, and sign-off processes, including lab correlation.
Perform Power Distribution Network (PDN) analyses, including model generation and time-domain simulation.
Work closely with backend, package, and board design teams for bump-out and ball-out optimization.
Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond, ensuring signal and power integrity best practices.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devicesSilicon One. Our team operates in a startup-like environment within a stable and leading corporation.

Your Impact:
Craft and develop software driving the world's most complex infrastructures.
Gain intimate knowledge of world-class silicon and programming models.
Work with architecture and design teams to define the next generation of ASIC products being developed.

As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

What You'll Do:
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are excited to announce that the Silicon One team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!

You'll be joining Silicon One Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs.

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

In this role, you will:

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed.

Location: Caesarea, Israel.