רובוט
היי א אי
stars

תגידו שלום לתפקיד הבא שלכם

לראשונה בישראל:
המלצות מבוססות AI שישפרו
את הסיכוי שלך למצוא עבודה

מהנדס מחשבים

מסמך
מילות מפתח בקורות חיים
סימן שאלה
שאלות הכנה לראיון עבודה
עדכון משתמש
מבחני קבלה לתפקיד
שרת
שכר
משרות על המפה
 
בדיקת קורות חיים
VIP
הפוך ללקוח VIP
רגע, משהו חסר!
נשאר לך להשלים רק עוד פרט אחד:
 
שירות זה פתוח ללקוחות VIP בלבד
AllJObs VIP

חברות מובילות
כל החברות
כל המידע למציאת עבודה
5 טיפים לכתיבת מכתב מקדים מנצח
נכון, לא כל המגייסים מקדישים זמן לקריאת מכתב מק...
קרא עוד >
הטבות ובונוסים בעבודה בחברות הייטק
מכון כושר צמוד, חדר אוכל משובח, חדר משחקי וידאו...
קרא עוד >
כיצד מקימים חברת סטארט אפ?
סטארטאפיסטים לשעבר מחלקים עצות כיצד להקים חברת ...
קרא עוד >
לימודים
עומדים לרשותכם
מיין לפי: מיין לפי:
הכי חדש
הכי מתאים
הכי קרוב
טוען
סגור
לפי איזה ישוב תרצה שנמיין את התוצאות?
Geo Location Icon

לוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
our company is a global leader in control systems for our computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. at qm, we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. qms hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. we are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. our company is backed by globally recognized venture capital sponsors, including tlv partners, battery ventures, red dot capital partners, avigdor willenz investment group, harel insurance, and others.
we are looking for an excellent design engineer to join our team and build qm's state-of-the-art control and orchestration platform. we are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
responsibilities:
learning system and sw requirements for proper implementation of hw-sw interface
designing a configurable and very low-latency challenging rtl
bringing the state-of-the-art fpga to its limits with regards to logic & timing optimization
end2end ownership of the entire coding process (arch->uarch->design->implementation)
Requirements:
requirements:
bsc in electrical/computer engineering or relevant military background
at least 4 years of experience
proven track record in rtl coding with system verilog
experience with system verilog
vcs, vivado - advantage
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593029
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
description
our company is a global leader in hybrid control systems for quantum computing, a field on the verge of exponential growth.
our innovative hardware and software offer a groundbreaking approach to controlling quantum computers, scaling from individual qubits to arrays of thousands.
at the heart of qm is a passionate, ambitious team committed to transforming the construction and operation of quantum computers. our deep understanding of customer needs drives us to deliver unmatched solutions in this revolutionary field.
we are looking for a highly experienced a hands-on compiler engineer who embodies ambition and positivity.
someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
responsibilities:
develop qm's compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
take on complex optimization challenges at the core of our unique compiler, focusing on Real-Time applications, hybrid quantum/classical algorithms, and parallel processing.
conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.
Requirements:
requirements:
at least 5 years of hands-on programming experience - must.
bsc. in Computer Science, computer engineering, mathematics, or any relevant scientific field (advanced degrees are an advantage) - must.
experience in computer architecture, assembly language, and low-level programming concepts - advantage.
experience working in a multidisciplinary environment - advantage.
familiarity with mlir/llvm - advantage.
a motivated and resourceful problem solver with a passion for tackling complex technical challenges, especially in hardware-oriented environments.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8593016
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
collaborate with architecture, design, and verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing TEST solutions for new high performance computing (hpc) products in advanced process technologies.
verify TEST solutions on pre-silicon models (simulation or emulation) and develop ate TEST modules, dc tests, binning, production flows, and characterization flows.
develop and validate TEST programs on ate platforms for new product integration (npi) in preparation for high volume manufacturing (hvm), working with ate vendors.
support product sustainability, including volume data analysis of screening and characterization data, TEST time and yield improvements, TEST escapees and return merchandise authorizations (rmas) assessments, failure localization, containment measure implementation, and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
develop tools, flows, and methodologies to continuously improve and automate the testing.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in design, TEST, manufacturing, or process engineering.
experience in pre-silicon validation, TEST content generation, ate program development, and post-silicon enabling from npi through hvm.
experience in asic TEST methodologies (e.g., mbist, atpg, dft, serdes, and sensors).
experience in Python, JAVA, C #, or C / C ++, and advantest or teradyne ate platforms.
preferred qualifications:
experience in creating end-to-end manufacturing TEST strategies for pcba and systems that cover structural through functional and system tests.
experience in ate hardware design and proliferation such as load boards/probe cards, handler kits, sockets, and thermal control solutions.
experience in developing or integrating manufacturing TEST hardware using electrical and thermo-mechanical components.
experience in developing automations for pre-silicon verification and post-silicon TEST -generation/ TEST -program domains.
experience with cpu/gpu SOC architecture, design, validation, and debug.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592956
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, register-transfer level (rtl) design concepts, and languages such as verilog or system verilog.
experience in logic design and debug with design verification (dv).
experience with microarchitecture and specifications.
preferred qualifications:
experience with logic synthesis techniques to optimize register-transfer level (rtl) code, performance and power as well as low-power design techniques.
experience with design sign off and quality tools (lint, cdc, vclp etc.).
experience in a scripting language like Python or PERL.
knowledge of SOC architecture and assertion-based formal verification.
knowledge of one of these areas, pcie, ucie, ddr, axi, arm processors family.
knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592940
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will contribute in all phases of application-specific integrated circuit (asic) designs from design specification to production. you will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SOC /rtl. you will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhdl), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
8 years of experience in technical leadership.
experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
experience developing rtl for asic subsystems.
preferred qualifications:
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience in tcp, ip, ethernet, pcie and dram including network on chip ( NOC ) principles and protocols (axi, ace, and chi).
experience architecting networking switches, end points, and hardware offloads.
understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592921
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.as a design & power methodology team manager within the server chip design team, you will be responsible of managing and leading design and power methodologies from ip to SOC, pre and post silicon. you will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.you will work closely with cad vendors and internal teams to develop lead design and power methodology and execution.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead flow and methodology development and assimilation across multiple groups. work closely with cad tool providers as well as internal cad teams.
plan, execute, track progress, assure quality, and report status.
work closely with internal customers and support multiple activities and deliverables.
drive design methodologies such as design construction, cdc, rdc, sdc. drive power at: ip and SOC rtl/gate level optimization, estimation, correlation.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in rtl design cycle ip and SOC.
8 years of experience in team management.
experience with design methodologies, structural checks, and power estimation/optimization.
preferred qualifications:
experience with synthesis techniques to optimize register-transfer level (rtl) code, performance and power as well as low-power design techniques.
experience with a scripting language like Python or PERL.
experience with design for TEST and its impact on design and physical design.
knowledge of ip and SOC architecture.
knowledge of physical design techniques: sdc, synthesis, emir, etc.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592897
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Ramat Gan
Job Type: Full Time
our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. our products need to handle information at massive scale, and extend well beyond web search. we're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data Storage, security, artificial intelligence, Natural Language Processing, UI design and mobile; the list goes on and is growing every day. as a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. we need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the Full-Stack as we continue to push technology forward.
the team owns the fundamental architecture and shared services that underpin the entire chronicle security operations, automation, and response (soar) product. our focus is on the "how" of the product, ensuring that every case, investigation, and automated response flow executes on a high-performing engine.our cloud accelerates every organizations ability to digitally transform its business and industry. we deliver enterprise-grade solutions that leverage our cutting-edge technology, and tools that help developers build more sustainably. customers in more than 200 countries and territories turn to our cloud as their trusted partner to enable growth and solve their most critical business problems.
responsibilities
write product or system development code.
lead the design and implementation of scalable backend services that support chronicle soars high-concurrency investigation and agentic response flows.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
build and optimize internal tools and ci/cd pipelines to streamline resource orchestration and empower feature teams to deploy with confidence.
drive the adoption of enterprise-grade patterns, ensuring that new features adhere to standards for modularity, performance, and security across the microservices ecosystem.
Requirements:
minimum qualifications:
bachelors degree or equivalent practical experience.
2 years of experience with software development or 1 year of experience with an advanced degree in an industry setting.
2 years of experience with developing large-scale infrastructure, distributed systems or networks, or experience with compute technologies, Storage or hardware architecture.
preferred qualifications:
master's degree or phd in Computer Science or related technical fields.
3 years of experience with software development in go, Python or C # programming languages, or 2 year of experience with an advanced degree.
2 years of experience with data structures and algorithm.
experience developing accessible technologies.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592886
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will be part of a team developing application-specific integrated circuits (asics) used to accelerate networking in data centers. you will have multiple responsibilities in areas such as project definition, design, and implementation. you will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.you will also be responsible for performance analysis for a networking stack using your knowledge.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead an asic subsystem.
understand how it interacts with software and other asic subsystems to implement data center networks.
define hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
experience developing register-transfer level (rtl) for asic subsystems.
experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience working with software teams optimizing the hardware/software interface.
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience architecting networking switches, end points, and hardware offloads.
experience in transmission control protocol (tcp), ip, ethernet, peripheral component interconnect express (pcie) and dynamic random access memory (dram) including network on chip ( NOC ) principles and protocols (e.g., axi, ace, and chi).
understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.
proficiency in procedural programming language (e.g., C ++, Python, go).
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592888
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.
Requirements:
minimum qualifications:
bachelor's degree in Computer Science, computer engineering, or electrical engineering, or equivalent experience.
8 years of experience in SOC or central processing unit (cpu) performance and power modeling, analysis, and debugging.
experience with computer architecture, focusing in the areas like interconnects, traffic quality of service (qos), distributed caches, and i/o flows.
experience in programming languages such as C, C ++, or similar.
experience in identifying, troubleshooting, and solving performance problems.
preferred qualifications:
experience with hardware description languages like verilog or systemverilog.
experience in one or more functional areas, such as coherent fabrics (e.g., amba chi/axi), memory controllers (e.g., lpddr5, ddr5), or i/o controllers (e.g., pcie, cxl).
experience in productizing features that enhance the performance or power characteristics of a design.
experience in building fast, accurate SOC /cpu performance models in C ++.
experience in pre-silicon and post-silicon analysis and debugging.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592868
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
lead an asic subsystem and understand how it interacts with software and other asic subsystems to implement groundbreaking data center networks.
define high-performance hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
implement designs in systemverilog.
collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking asics from specification to production.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience architecting networking switches, end points, and hardware offloads.
experience working with design networking like remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience working with software teams optimizing the hardware/software interface.
experience in tcp, ip, ethernet, pcie, dram, network on chip ( NOC ) principles and protocols.
experience in a procedural programming language (e.g., C ++, Python, go).
understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592849
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
perform register-transfer level (rtl) coding (coding and debug in verilog, systemverilog), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power closure activities.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, rtl design concepts, and languages, such as verilog or systemverilog.
experience with logic synthesis techniques to optimize rtl code, performance and power, as well as low-power design techniques.
experience with design sign-off and quality tools (e.g., lint, cdc, etc.).
experience with SOC or ip architecture.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering, Computer Science, or a related field.
knowledge of high-performance and low-power design techniques, assertion-based formal verification, field-programmable gate array (fpga) and emulation platforms, and SOC architecture.
knowledge in one of the following areas such as double data rate (ddr)/low power double data rate (lpddr), high-bandwidth memory (hbm).
excellent problem-solving and debugging skills.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592851
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592844
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
as a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. you develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of google users.
as a cmos technologist and foundry engineer, you'll be part of the growing chip design team. in this role, you'll be responsible for driving cmos (complementary metal oxide semiconductor) foundry partners, intellectual property (ip), and chip design and implementation teams to perform cmos transistor scaling and power/performance analysis (ppa), and producing technology roadmap benchmarks. you will also be involved in interfacing and driving our design ip partners.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
engage with cmos foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform ppa simulations on benchmark circuits.
work with fab partners on device and circuit level TEST structures, TEST chips, and characterization and correlation of silicon data. you will use the results of this work to influence design optimizations.
work with ip partners, design, and physical design teams to design advanced cmos.
work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
work with our commercial and product teams on foundry and ip vendor management, track technology roadmaps, and determine appropriate technology and ip integration strategies.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, related field or equivalent practical experience.
8 years of experience in foundry design kits bring-up, spice simulations, signal/power analysis with advanced cmos finfet nodes.
experience in semiconductor/device engineering, process development, or electrical characterization of device/circuits.
preferred qualifications:
master's degree or phd in electrical engineering or physics with an emphasis on semiconductor materials or device physics.
experience in SOC chip physical implementation.
understanding of analog and digital circuits such as plls, high speed io, cache and standard cell libraries in advanced cmos finfet nodes.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592831
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive cutting-edge tpu (tensor processing unit) technology that powers google's most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
as a design technology co-optimization (dtco) engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. you will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.in this role, you will conduct place and route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. you will collaborate with foundry, ip, and architecture teams to identify power, performance, and area (ppa) bottlenecks and drive system technology co-optimization (stco) initiatives.your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify ppa gains. by navigating the trade-offs between process complexity and design performance, you will ensure googles hardware achieves efficiency and power density.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
execute high-fidelity place and route experiments to evaluate the ppa impact of advanced process features, library architectures, and design rule variations on datacenter-class ip.
drive design technology co-optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track he
דרישות:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in physical design (rtl-to-gds) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
experience with industry-standard place and route (p&r) tools and static timing analysis (sta) tools.
experience in cmos device physics, finfet/nanosheet architectures, and the impact of layout parasitics on ppa.
experience in scripting and automation using tcl and Python (or PERL ) to manage design sweeps and data extraction.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering or Computer Science, with an emphasis on computer architecture.
experience in design technology co-optimization (dtco), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
experience working with major foundry technology files (pdks) and interpreting design rule manuals (drm) to guide physical im המשרה מיועדת לנשים ולגברים כאחד.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592810
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
with your technical expertise you will manage project priorities, deadlines, and deliverables. you will design, develop, TEST, deploy, maintain, and enhance software solutions.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are  cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
create software solutions that improve the hardware post-silicon testing process through automation. this includes, but is not limited to, developing and maintaining an automatic TEST equipment (ate) program development infrastructure for both production and development environments.
propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon TEST flow, from design for testing (dft) to ate.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
5 years of industry experience with high performance, systems, and debugging.
5 years of experience in ate tools, flows and methodologies.
experience in code and system health, diagnosis and resolution, and software TEST engineering.
experience in ate TEST development, from dft/design verification (dv) to ate (e.g., reset, automatic TEST pattern generation (atpg), memory built-in self TEST (mbist), or functional content development to ate patterns).
preferred qualifications:
experience in ate TEST method library development taking ate low level drivers and developing automated solutions.
understanding of object oriented programming and functional programming.
excellent software skills and design practices.
This position is open to all candidates.
 
Show more...
הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592788
סגור
שירות זה פתוח ללקוחות VIP בלבד
משרות שנמחקו