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משרה בלעדית
1 ימים
דרושים בReady
Job Type: Full Time and Hybrid work
We are looking for a Senior Verification engineer to join our team. 

Job Description:
 The role includes defining verification strategies, building environments, and ensuring coverage closure for complex designs.
You will work closely with design and architecture teams throughout the full development lifecycle.
Requirements:
- B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
 - 7+ years of hands-on experience in VLSI Verification
 - Strong knowledge of SystemVerilog and UVM
 - Experience with C / C ++ and Python or PERL - advantage
-  Background in RTL analysis and complex logic verification - advantage
This position is open to all candidates.
 
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הגשת מועמדות
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8720275
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2 ימים
דרושים באמרל בע"מ
מיקום המשרה: כרמיאל
סוג משרה: משרה מלאה
אחריות על תכנון, פיתוח וביצוע בדיקות (BIT ( TEST in-Built למערכות משובצות מחשב.
עבודה בשיתוף פעולה עם מהנדסי מערכת ותוכנה כדי להבטיח איכות ומהימנות של המערכות.
איתור ותיקון תקלות במערכות.
כתיבת דוחות בדיקה ותיעוד.

תפקידים ואחריות:
פיתוח ותחזוקה של בדיקות BIT.
ביצוע בדיקות ותיעוד תוצאות.
שיתוף פעולה עם צוות הפיתוח והנדסת המערכת.
כתיבת דוחות בדיקה
דרישות:
טכנאי/הנדסאי או רקע וניסיון טכני מוכחים

נכונות לעבודה;Hands-On

יכולת עבודה עצמאית וביצוע משימות מוגדרות ללא צורך בהנחיה מתמדת

ניסיון בתפעול מערכות מתקדמות

ניסיון בביצוע ניסויים למערכות מולטידיספלינאריות מורכבות

ניסיון עבודה בתקשורת RF / ניווט / מכלולי חישה - יתרון המשרה מיועדת לנשים ולגברים כאחד.
 
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8521426
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דרושים בSpecial Job – חברת השמה בהייטק
Israel company developing and selling energy measurement and analysis systems
including meters, Power quality analyzers and fault analyzers for industrial/commercial customers in
more than 80 countries throughout five continents, is looking for cyber architect IOT.

Location: Jerusalem Work Model: On-site Team Size: [6-10] QA Engineers Reports to: QA Manager

We are looking for a QA Engineer to join our QA team.

Position duties and responsibilities:
Perform functional tests and verification of power measurement devices
Write TEST documents and TEST plans
Analyze results, reporting and qualification of issues
Build TEST setups and manage LAB infrastructure
Work closely with the development teams
Requirements:
At least 3 years of experience in testing and verification of products
Communication protocols practical knowledge - TCP/IP, Modbus, (more protocols - advantage)
Serial communication - hands-on experience
Proven experience in writing TEST documents
Jira or other Quality Management Systems - hands-on experience
BSc in Electric & Electronic Engineering - advantage
Perfect Hebrew and English reading and writing skills, more languages - advantage
This position is open to all candidates.
 
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8554698
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
משרה בלעדית
2 ימים
דרושים בQpoint Technologies
סוג משרה: משרה מלאה
מחפש/ת את האתגר הבא בעולם ה- RF והמיקרוגל?

לחברה טכנולוגית מובילה באזור ירושלים דרוש/ה מהנדס/ת או הנדסאי/ת אלקטרוניקה לתפקיד מרכזי בצוות האינטגרציה והבדיקות. הזדמנות להשתלב בסביבה טכנולוגית מתקדמת, לעבוד עם מערכות מורכבות וציוד בדיקה מהמתקדמים בתחום, ולהיות חלק מתהליך העברת מוצרים חדשניים מפיתוח לייצור.

מה כולל התפקיד?
הובלת תהליכי אינטגרציה ובדיקות סופיות למערכות ורכיבים בתחום ה- RF והמיקרוגל.
ביצוע כיוונים עדינים ואופטימיזציה של מכלולים אלקטרוניים.
איתור, ניתוח ופתרון תקלות ברמת הרכיב והמערכת.

משרה מלאה א-ה
דרישות:
הנדסאי/ת או מהנדס/ת אלקטרוניקה - חובה.
ניסיון קודם באינטגרציה, בדיקות או Bring-Up של מערכות אלקטרוניות - חובה.
ניסיון בעבודה עם צב"ד מתקדם - חובה.
יכולת גבוהה בקריאת סכמות חשמליות ושרטוטים טכניים.
עברית ברמת שפת אם ואנגלית טכנית טובה.
מגורים באזור ירושלים והסביבה.
ניסיון במערכות RF ומיקרוגל - יתרון משמעותי. המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדות
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4 ימים
Location: Caesarea
Job Type: Full Time
This is an opportunity for you to integrate with end customers in both hands-on and advisory roles to solve technical challenges with various test cell set ups. To work on the bleeding edge of semi-test technology and to sharpen your relationship management skills while developing strategic partnerships that will round out your arsenal of 3rd party vendor provided products that enhance our solutions.



Key Responsibilities

Influence next generation ATE tester and Test Cell product roadmaps
Work directly with leading edge semiconductor companies supporting their efforts to develop Test Cells to enable advanced chip designs to market
Responsible for the mastering of Teradyne Test Cell products, product applications and policies.
Provide expert advice to customers, Sales, FAEs and support staff while working closely with sales/marketing management and test cell staff to ensure that relevant technical information is promptly and accurately communicated
Develop strategic relationships throughout our sales team and customer's key technical decision makers
Work with marketing on technical differentiation and generation of technical proofs for use by the customer team.
Develop, present, and respond to proposals for specific customer requirements
Coordinate, develop and deliver product demonstrations which display the value of our solutions
Works closely with customers to define new test cell opportunities and support existing sustainment activities. Travel requirements could be 25% or greater.
Lead in new product introduction with integration at customer sites with project management, hands-on integration, and training activities.
Support emerging markets, acting as a liaison between customers and the engineering, marketing, and operations teams to help with their product development.
Keep informed and present updates on competitors, industry news and trends, products services, relevant information about legacy, existing, emerging technologies, and the latest product-line development
Requirements:
BSME or BSEE or equivalent. MBA is a plus.
5+ years experience in the semiconductor capital equipment/ATE industry/Test Cell Products.
Solid electromechanical and machine design/applications development skills.
Experience with Analog, Mixed-Signal, complex SOC, RF, Memory testing
Strong understanding in PCB and signal delivery design
Strong understanding and operational knowledge of semiconductor material handling equipment (wafer prober and final test handlers)
Strong understanding of semiconductor device packaging and contact technologies (probe cards and contactors)
Basic understanding of Software development
Fundamental understanding of Release to Market (RTM) and Overall Equipment Efficiency (OEE) principals
Fundamental understanding of ATE material handling equipment is desired
Business background or equivalent marketing and/or sales experience desired
Experience with CAD software, Pro/Engineer or SolidWorks is a plus Fluent in English and Hebrew
Strong interpersonal and communications skills
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8721455
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Verification Vision Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, youll work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in our edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., System Verilog/Specman), design verification methodologies (e.g., UVM) and chip design flow.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
10 years of experience managing verification teams.
Experience in chip design/verification of high performance AI/ML accelerators.
Experience with industry verification techniques, including complementary techniques such as formal verification, and emulation.
Experience in low power verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717585
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717566
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תיאור
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior CPU Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717535
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717519
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time and Hybrid work
Required ASIC Design & Verification Engineer
Meet the Team
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.
Requirements:
Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering from a top university
3+ years of experience in the filed
knowledge with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8717107
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29/06/2026
Location: Merkaz
Job Type: Full Time
abra R&D is seeking for a Verification Engineer. We are looking for an Adaptable Verification Engineer who can move across blocks and tasks, partner with design/FPGA/architecture, and own floating assignments with partial specs. ?Key Responsibilities:
* Build/maintain SystemVerilog/UVM environments; write testbenches, simulations, and regressions.
* Analyze specs- create verification plans; drive debug and bug fixing to closure.
* Track functional/code coverage; document flows and improve team productivity.
* Context?switch across blocks; support integration and ad?hoc scripting/automation.
Requirements:
* B.Sc. in EE/CE (or related).
* 3+ years of verification experience in ASIC/SoC.
* Strong SystemVerilog/UVM; experience with Verdi/Questa/VCS.
* Proven self?learning, flexibility, and ownership of undefined work; clear teamwork/communication. Nice to Have
* Protocols: AMBA/AXI/AHB, PCIe, Ethernet.
* Scripting: Python, Perl, Tcl.
* Tools: Git, Jira.
This position is open to all candidates.
 
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Location: Giv'atayim
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.
Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.
Requirements:
6+ years of verification experience, including hands-on experience building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in verification languages such as SystemVerilog, UVM, Spaceman
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
Bachelor degree in electrical engineering or computer science, or equivalent experience.
This position is open to all candidates.
 
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23/06/2026
Location: Yokne`am
Job Type: Full Time
We are looking for an experienced Team Lead for the NIC FW verification infrastructure team. In this role, you will lead the verification infrastructure - ensuring testing infrastructure stability, scalability, and continuous improvement - while guiding the development of advanced modules and methodologies. You will be responsible for driving the teams technical direction, supporting the evaluation of data and control path for new features, and ensuring high-quality deliverables that meet the expectations of industry-leading customers. As a leader, you will mentor and grow a team of engineers, foster a culture of ownership and execution, and collaborate closely with our networking NIC FW teams.

What you will be doing:

Lead and drive team execution end-to-end, combining managerial ownership with hands-on technical contribution - including ownership of the verification testing domain, its flows, coverage and the regression cycle.

Develop deep expertise in our technologies, with a strong focus on FW functionality with corresponding interfaces with HW and SW.

Drive team execution by setting clear priorities, removing blockers, and ensuring high-quality, timely delivery - while maintaining a high bar for technical excellence and clearly communicating priorities, trade-offs, and status to stakeholders.

Define and continuously improve testing methodologies, including leading retrospectives for missed bugs to identify gaps - driving actionable changes to test coverage, flows, and verifiers.

Act as a technical leader within the team, contributing to design discussions, mentoring engineers, and actively participating in high-level design and code reviews.
Requirements:
What we need to see:

B.Sc. in Software Engineering, Computer Engineering, Electrical Engineering, or Computer Science.

3+ years of experience in an engineering management or team leadership role, with a strong hands-on technical background. 6+ overall years of experience as an engineer.

Strong coding skills with deep understanding of OOP principles and software design.

Ability to operate effectively in a fast-paced, dynamic environment, balancing execution with continuous improvement.

Demonstrated leadership qualities - ownership, initiative, problem-solving mindset, and the ability to drive results independently and as part of a team. Excellent verbal and written communication skills in English, with the ability to clearly articulate priorities and align with stakeholders.

f
Ways to stand out from the crowd:

Deep familiarity with c++.

Familiarity with regression concepts, testing flows, and CI practices.

Knowledge of Networking protocols.

Working with Git, Gerrit, Jenkins, Docker.

Experience in working in an agile approach.
This position is open to all candidates.
 
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